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ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-8
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9.3.1 Restrictions on AXI transfers
The Cortex-R4 AXI master interface applies the following restrictions to the AXI transactions
it generates:
• A burst never transfers more than 32 bytes.
• The burst length is never more than 8 transfers.
• No transaction ever crosses a 32-byte boundary in memory. See AXI transaction splitting
on page 9-16.
• FIXED bursts are never used.
• The write address channel always issues INCR type bursts, and never WRAP or FIXED.
• WRAP type read bursts, see Linefills on page 9-13:
— are used only for linefills (reads) of Cacheable Normal non-shared memory
— always have a size of 64 bits, and a length of 4 transfers
— always have a start address that is 64-bit aligned.
• If the transfer size is 8 bits or 16 bits then the burst length is always 1 transfer.
• The transfer size is never greater than 64 bits, because it is a 64-bit AXI bus.
• Instruction fetches, identified by ARPROT[2], are always a 64 bit transfer size, and never
locked or exclusive.
• Transactions to Device and Strongly Ordered memory are always to addresses that are
aligned for the transfer size. See Strongly Ordered and Device transactions.
• Exclusive and Locked accesses are always to addresses that are aligned for the transfer
size.
• Write data is never interleaved.
• In addition to the above, there are various limitations to the ID values that the AXI master
interface uses. See Identifiers for AXI bus accesses on page 9-4.
9.3.2 Strongly Ordered and Device transactions
A load or store instruction to or from Strongly Ordered or Device memory always generates
AXI transactions of the same size as implied by the instruction. All accesses using
LDM
,
STM
,
LDRD
,
or
STRD
instructions to Strongly Ordered or Device memory occur as 32-bit transfers.
LDRB
Table 9-4 shows the values of ARADDRM, ARBURSTM, ARSIZEM, and ARLENM for a
Non-cacheable
LDRB
from bytes 0-7 in Strongly Ordered or Device memory.
Table 9-4 Non-cacheable LDRB
Address[2:0] ARADDRM ARBURSTM ARSIZEM ARLENM
0x0
(byte 0)
0x00
Incr 8-bit 1 data transfer
0x1
(byte 1)
0x01
Incr 8-bit 1 data transfer
0x2
(byte 2)
0x02
Incr 8-bit 1 data transfer
0x3
(byte 3)
0x03
Incr 8-bit 1 data transfer