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ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-39
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11.6 Debug events
A processor responds to a debug event in one of the following ways:
• ignores the debug event
• takes a debug exception
• enters debug state.
This section describes:
• Software debug event
• Halting debug event on page 11-40.
• Behavior of the processor on debug events on page 11-40
• Debug event priority on page 11-40
• Watchpoint debug events on page 11-40.
11.6.1 Software debug event
A software debug event is any of the following:
• A watchpoint debug event. This occurs when:
— The data address for a load or store matches the watchpoint value.
— All the conditions of the WCR match.
— The watchpoint is enabled.
— The linked context ID-holding BRP, if any, is enabled and its value matches the
context ID in CP15 c13. See Chapter 4 System Control Coprocessor.
— The instruction that initiated the memory access is committed for execution.
Watchpoint debug events are only generated if the instruction passes its condition code.
• A breakpoint debug event. This occurs when:
— An instruction was fetched and the instruction address or the CP15 Context ID
register c13 matched the breakpoint value.
— At the same time the instruction was fetched, all the conditions of the BCR for
unlinked context ID breakpoint generation matched the I-side control signals.
— The breakpoint is enabled.
— The instruction is committed for execution. These debug events are generated
whether the instruction passes or fails its condition code.
• A BKPT debug event. This occurs when a
BKPT
instruction is committed for execution.
BKPT
is an unconditional instruction.
• A vector catch debug event. This occurs when:
— An instruction was prefetched and the address matched a vector location address.
This includes any kind of prefetch, not only the ones because of exception entry.
— At the same time the instruction was fetched, the corresponding bit of the VCR was
set, that is, the vector catch is enabled.
— The instruction is committed for execution. These debug events are generated
whether the instruction passes or fails its condition code.