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Introduction
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-17
ID013010 Non-Confidential, Unrestricted Access
1.7 Execution pipeline stages
The following stages make up the pipeline:
• the Fetch stages
• the Decode stages
• an Issue stage
• the three or four Execution stages.
Figure 1-2 shows the Fetch and Decode pipeline stages of the processor and the pipeline
operations that can take place at each stage.
Figure 1-2 Processor Fetch and Decode pipeline stages
The names of the pipeline stages and their functions are:
Fe Instruction fetch where data is returned from instruction memory.
Pd Pre-decode where instructions are formatted and branch prediction occurs.
De Instruction decode.
Figure 1-3 shows the Issue and Execution pipeline stages for the Cortex-R4 processor.
Figure 1-3 Cortex-R4 Issue and Execution pipeline stages
Figure 1-4 on page 1-18 shows the Issue and Execution pipeline stages for the Cortex-R4F
processor.
Fe1 Fe2 Pd De
Instruction
decode
Predicted branches and returns
Instruction
formatting
branch
predicting
2
nd
fetch
stage
1
st
fetch
stage
Register
read,
address
generation,
and
instruction
issue
EX1
DC1
Exception flush and mispredicted
indirect branches
EX1
DC2
Load/store
pipeline
Data
processing
pipeline
Iss Ex1 Ex2 Wr
Ret
Mispredicted direct branches
Wr