Filter
Top Products
Introduction
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-19
ID013010 Non-Confidential, Unrestricted Access
1.8 Redundant core comparison
The processor can be implemented with a second, redundant copy of most of the logic. This
second core shares the input pins and the cache RAMs of the master core, so only one set of
cache RAMs is required. The master core drives the output pins and the cache RAMs.
Comparison logic can be included during implementation which compares the outputs of the
redundant core with those of the master core. If a fault occurs in the logic of either core, because
of radiation or circuit failure, this is detected by the comparison logic. Used in conjunction with
the RAM error detection schemes, this can help protect the system from faults. The inputs
DCCMINP[7:0] and DCCMINP2[7:0] and the outputs DCCMOUT[7:0] and
DCCMOUT2[7:0] enable the comparison logic inside the processor to communicate with the
rest of the system.
ARM provides example comparison logic, but you can change this during implementation. If
you are implementing a processor with dual-redundant cores, contact ARM for more
information. If you are integrating a Cortex-R4 macrocell with dual-redundant cores, contact the
implementer for more details.