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ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-46
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11.8.3 Executing instructions in debug state
In debug state, the processor executes instructions issued through the Instruction Transfer
Register (ITR). Before the debugger can force the processor to execute any instruction, it must
enable this feature through DSCR[13].
While the processor is in debug state, it always decodes instructions from the ITR as per the
ARM instruction set, regardless of the value of the T and J bits of the CPSR.
The following restrictions apply to instructions executed through the ITR while in debug state:
• with the exception of branch instructions and instructions that modify the CPSR, the
processor executes any ARM instruction in the same manner as if it was not in debug state
• the branch instructions
B
,
BL
,
BLX(1)
, and
BLX(2)
are Unpredictable
• certain instructions that normally update the CPSR are Unpredictable
• instructions that load a value into the PC from memory are Unpredictable.
11.8.4 Writing to the CPSR in debug state
The only instruction that can update the CPSR while in debug state is the
MSR
instruction. All
other ARMv7 instructions that write to the CPSR are Unpredictable, that is, the
BX
,
BXJ
,
SETEND
,
CPS
,
RFE
,
LDM(3)
, and data processing instructions with Rd==R15 and S==1.
The behavior of the CPSR forms of the
MSR
and
MRS
instructions in debug state is different to their
behavior in normal state:
• When not in debug state, an
MSR
instruction that modifies the execution state bits in the
CPSR is Unpredictable. However, in debug state an MSR instruction can update the
execution state bits in the CPSR. An Instruction Synchronization Barrier (ISB) sequence
must follow a direct modification of the execution state bits in the CPSR by an
MSR
instruction.
• When not in debug state, an
MRS
instruction reads the CPSR execution state bits as zeros.
However, in debug state an
MRS
instruction returns the actual values of the execution state.
The debugger must execute an
ISB
sequence after it writes to the CPSR execution state bits using
an
MSR
instruction. If the debugger reads the CPSR using an
MRS
instruction after a write to any
of these bits, but before an
ISB
sequence, the value that
MRS
returns is Unpredictable. Similarly,
if the debugger forces the processor to leave debug state after an
MSR
writes to the execution state
bits, but before any
ISB
sequence, the behavior of the processor is Unpredictable.
11.8.5 Privilege
When the processor is in debug state, ARM instructions issued through the ITR are subject to
different rules about whether they can perform privileged actions. The general rule is that all
instructions and operations are permitted in debug state.
11.8.6 Accessing registers and memory
The processor always accesses register banks and memory as indicated by the CPSR mode bits,
in both normal and debug state. For example, if the CPSR mode bits indicate the processor is in
User mode, ARM register reads and returns the User mode banked registers, and memory
accesses are presented to the MPU as not privileged.