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Processor Signal Descriptions
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-14
ID013010 Non-Confidential, Unrestricted Access
Table A-10 shows the B1TCM port signals.
B0TCLATEERROR Input CLKIN
Late error from B0TCM
a
B0TCRETRY Input CLKIN
Access to B1TCM must be retried
a
B0TCADDRPTY Output CLKIN
Parity formed from B0TCM address output
b
B0TCWE Output CLKIN Write enable for B0TCM
B0TCEN0 Output CLKIN Enable for B0TCM lower word, bit range [31:0]
B0TCEN1 Output CLKIN Enable for B0TCM upper word, bit range [64:32]
B0TCADDR [22:3] Output CLKIN Address for B0TCM data RAM
B0TCBYTEWR [7:0] Output CLKIN Byte strobes for direct write
B0TCSEQ Output CLKIN B0TCM RAM access is sequential
B0TCDATAOUT [63:0] Output CLKIN Write data for B0TCM data RAM
B0TCPARITYOUT [13:0] Output CLKIN Write parity or ECC code for B0TCM
B0TCACCTYPE[2:0] Output CLKIN Determines access type:
b001 = Load/Store
b010 = Fetch
b100 = DMA
b100 = MBIST
c
.
a. This signal is ignored when bit [1] of the Auxiliary Control Register is set to 0, see c1, Auxiliary Control Register
on page 4-38.
b. Only generated if the processor is configured to include TCM address bus parity.
c. The MBIST interface has no way of signalling a wait. If it is accessing the TCM, and the TCM signals a wait, the
AXI slave pipeline stalls and the data arrives later. However, no signal is sent to the MBIST controller to indicate
this.
Table A-9 B0TCM port signals (continued)
Name Direction Clocking Description
Table A-10 B1TCM port signals
Name Direction Clocking Description
B1TCDATAIN [63:0] Input CLKIN Data from B1TCM
B1TCPARITYIN [13:0] Input CLKIN Parity or ECC code from B1TCM
B1TCERROR Input CLKIN
Error detected by B1TCM
a
B1TCRETRY Input CLKIN
Access to B1TCM must be retried
a
B1TCLATEERROR Input CLKIN
Late error from B1TCM
a
B1TCWAIT Input CLKIN Wait from B1TCM
B1TCADDRPTY Output CLKIN
Parity formed from B1TCM address output
b
B1TCWE Output CLKIN Write enable for B1TCM
B1TCEN0 Output CLKIN Enable for B1TCM lower word, bit range [31:0]
B1TCEN1 Output CLKIN Enable for B1TCM upper word, bit range [64:32]