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Integration Test Registers
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 13-7
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13.4.3 ITETMIF Register (ETM interface)
The ITETMIF Register at offset
0xED8
is write-only. Figure 13-1 shows the register bit
assignments.
Figure 13-1 ITETMIF Register bit assignments
Table 13-4 shows the fields when writing the ITETMIF Register. When this register is written
the appropriate output pins take the value written.
Reserved
31 543 0
EVNTBUS[28]
6
14 13 12 11 10 9 8 7 2 1
EVNTBUS[0]
ETMCID[31]
ETMCID[0]
ETMDD[63]
ETMDD[0]
ETMDA[31]
ETMDA[0]
ETMICTL[0]
ETMICTL[13]
ETMIA[1]
ETMIA[31]
ETMDCTL[0]
ETMDCTL[11]
15
EVNTBUS[46]
Table 13-4 ITETMIF Register bit assignments
Bits Name Function
[31:15] - Reserved. Write as zero.
[14] EVNTBUS[46]
Set value of the EVNTBUS[46] output pin
a
.
a. Not available on r0px revisions of the processor.
[13] EVNTBUS[28] Set value of the EVNTBUS[28] output pin.
[12] EVNTBUS[0] Set value of the EVNTBUS[0] output pin.
[11] ETMCID[31] Set value of the ETMCID[31] output pin.
[10] ETMCID[0] Set value of the ETMCID[0] output pin.
[9] ETMDD[63] Set value of the ETMDD[63] output pin.
[8] ETMDD[0] Set value of the ETMDD[0] output pin.
[7] ETMDA[31] Set value of the ETMDA[31] output pin.
[6] ETMDA[0] Set value of the ETMDA[0] output pin.
[5] ETMDCTL[11] Set value of the ETMDCTL[11] output pin.
[4] ETMDCTL[0] Set value of the ETMDCTL[0] output pin.
[3] ETMIA[31] Set value of the ETMIA[31] output pin.
[2] ETMIA[1] Set value of the ETMIA[1] output pin.
[1] ETMICTL[13] Set value of the ETMICTL[13] output pin.
[0] ETMICTL[0] Set value of the ETMICTL[0] output pin.