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Cycle Timings and Interlock Behavior
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-4
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ADD R3, R3, R1 LSL#6 ;plus one because Register R1 is Early
The following sequence where R1 is a Late Reg takes two cycles:
LDR R1, [R2] ;Result latency two minus one cycles
STR R1, [R3] ;no penalty because R1 is a Late register
The following sequence where R1 is a Very Early Reg takes four cycles:
ADD R3, R1, R2 ;Result latency one plus two cycles
LDR R4, [R3] ;plus two because register R3 is Very Early
14.1.2 Conditional instructions
Most instructions do not take more or fewer cycles to execute if they fail their condition codes.
The exceptions to this are:
• instructions that alter the PC, such as branches
• integer divide instructions, which require only one execute cycle.
The result latency of most instructions that fail their condition codes is one. The exceptions to
this are:
• all load and store instructions, which have their result latency unaffected
• integer divide instructions, which have a result latency of three.
14.1.3 Flag-setting instructions
Most instructions do not take more or fewer cycles to execute if they are flag-setting. The
exceptions to this are certain multiply instructions.
14.1.4 Definition of terms
Table 14-1 gives descriptions of cycle timing terms used in this chapter.
Table 14-1 Definition of cycle timing terms
Term Description
Memory Cycles This is the number of cycles during which an instruction sends a memory access to the cache.
Cycles This is the minimum number of cycles required to issue an instruction. Issue cycles that produce
memory accesses to the cache are included, so Cycles is always greater than or equal to Memory
Cycles.
Result Latency This is the number of cycles before the result of this instruction is available to a Normal Reg of the
following instruction. When the Result Latency of an instruction is greater than Cycles and the
following instruction requires the result, the following instruction stalls for a number of cycles equal
to Result Latency minus Cycles.
Note
The Result Latency is counted from the first cycle of an instruction.
Normal Reg The specified registers are required at the start of the Ex2 stage.
Late Reg The specified registers are not required until the start of the Wr stage. Subtract one cycle from the
Result Latency of the instruction producing this register.