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ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 15-11
ID013010 Non-Confidential, Unrestricted Access
Table 15-15 shows the timing parameters for the ETM interface output ports.
Table 15-16 shows the timing parameters for the test output ports.
Table 15-17 shows the timing parameters for the TCM interface output ports.
Table 15-15 ETM interface output ports timing parameters
Output delay
minimum
Output delay
maximum
Signal name
Clock uncertainty 50% ETMICTL[13:0]
Clock uncertainty 50% ETMIA[31:1]
Clock uncertainty 50% ETMDCTL[11:0]
Clock uncertainty 50% ETMDA[31:0]
Clock uncertainty 50% ETMDD[63:0]
Clock uncertainty 50% ETMCID[31:0]
Clock uncertainty 50% ETMWFIPENDING
Clock uncertainty 50% EVNTBUS[46:0]
Table 15-16 Test output ports timing parameters
Output delay
minimum
Output delay
maximum
Signal name
Clock uncertainty 50% MBISTDOUT[71:0]
Clock uncertainty 50% nVALIRQ
Clock uncertainty 50% nVALFIQ
Clock uncertainty 50% nVALRESET
Clock uncertainty 50% VALEDBGRQ
Table 15-17 TCM interface output ports timing parameters
Output delay
minimum
Output delay
maximum
Signal name
Clock uncertainty 45% ATCEN0
Clock uncertainty 45% ATCEN1
Clock uncertainty 45% ATCADDR[22:3]
Clock uncertainty 45% ATCBYTEWR[7:0]
Clock uncertainty 45% ATCSEQ
Clock uncertainty 45% ATCDATAOUT[63:0]
Clock uncertainty 45% ATCPARITYOUT[13:0]
Clock uncertainty 45% ATCACCTYPE[2:0]
Clock uncertainty 45% ATCWE