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ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-23
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Imprecise aborts
An imprecise abort, also known as an asynchronous abort, is one for which the exception is
taken on a later instruction to the instruction that generated the aborting memory access. The
abort handler cannot determine which instruction generated the abort, or the state of the
processor when the abort occurred. Therefore, imprecise aborts are normally fatal.
Imprecise aborts can be generated by store instructions to normal-type or device-type memory.
When the store instruction is committed, the data is normally written into a buffer that holds the
data until the memory system has sufficient bandwidth to perform the write access. This gives
read accesses higher priority. The write data can be held in the buffer for a long period, during
which many other instructions can complete. If an error occurs when the write is finally
performed, this generates an imprecise abort.
Imprecise abort masking
The nature of imprecise aborts means that they can occur while the processor is handling a
different abort. If an imprecise abort generates a new exception in such a situation, the r14_abt
and SPSR_abt values are overwritten. If this occurs before the data is pushed to the stack in
memory, the state information about the first abort is lost. To prevent this from happening, the
CPSR contains a mask bit to indicate that an imprecise abort cannot be accepted, the A-bit.
When the A-bit is set, any imprecise abort that occurs is held pending by the processor until the
A-bit is cleared, when the exception is actually taken. The A-bit is automatically set when abort,
IRQ or FIQ exceptions are taken, and on reset. You must only clear the A-bit in an abort handler
after the state information has either been stacked to memory, or is no longer required.
Only one pending imprecise abort of each imprecise abort type is supported. The processor
supports the following pending imprecise aborts:
• Imprecise external abort
If a subsequent imprecise external abort is signaled while another one is pending, the later
one is ignored and only one abort is taken.
• One TCM write external error for each TCM port.
• Cache write parity or ECC error.
If a subsequent cache parity or ECC error is signaled while another one is pending, the
later one is normally ignored and only one abort is taken. However, if the pending error
was correctable, and the later one is not correctable, the pending error is ignored, and one
abort is taken for the error that cannot be corrected.
Memory barriers
When a store instruction, or series of instructions has been executed to normal-type or
device-type memory, it is sometimes necessary to determine whether any errors occurred
because of these instructions. Because most of these errors are reported imprecisely, they might
not generate an abort exception until some time after the instructions are executed. To ensure
that all possible errors have been reported, you must execute a
DSB
instruction. Abort exceptions
are only taken because of these errors if they are not masked, that is, the CPSR A-bit is clear. If
the A-bit is set, the aborts are held pending.
Aborts in Strongly Ordered and Device memory
When a memory access generates an abort, the instruction generating that access is abandoned,
even if it has not completed all its memory accesses, and the abort exception is taken. The abort
handler can then do one of the following:
• fix the error and return to the instruction that was abandoned, to re-execute it