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Cycle Timings and Interlock Behavior
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-12
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14.7 Multiplies
Most multiply operations cannot forward their result early, except as the accumulate value for a
subsequent multiply. For a subsequent multiply accumulate the result is available one cycle
earlier than for all other uses of the result.
Certain multiplies require:
• more than one cycle to execute
• more than one pipeline issue to produce a result.
The multiplicand and multiplier are required as Early Regs because they are both required at the
end of the Iss stage.
Flag-setting multiplies followed by a conditional instruction interlock the conditional
instruction for one cycle, or two cycles if the instruction is a conditional multiply. Flag-setting
multiplies followed by a flag-setting instruction interlock the flag-setting instruction for one
cycle, unless the instruction is a flag-setting multiply in which case there is no interlock.
Table 14-9 shows the cycle timing behavior of example multiply instructions.
Table 14-9 Example multiply instruction cycle timing behavior
Example
instruction
Cycles Early Reg Late Reg Result latency
MUL(S)
2
<Rn>, <Rm>
-3
MLA(S)
,
MLS
2
<Rn>, <Rm> <Ra>
3
SMULL(S)
2
<Rn>, <Rm>
-3, 3
UMULL(S)
2
<Rn>, <Rm>
-3, 3
SMLAL(S)
2
<Rn>, <Rm> <RdLo>, <RdHi>
3, 3
UMLAL(S)
2
<Rn>, <Rm> <RdLo>, <RdHi>
3, 3
SMULxy
1
<Rn>, <Rm>
-2
SMLAxy
1
<Rn>, <Rm>
-2
SMULWy
1
<Rn>, <Rm>
-2
SMLAWy
1
<Rn>, <Rm>
-2
SMLALxy
2
<Rn>, <Rm> <RdLo>, <RdHi>
3, 3
SMUAD
,
SMUADX
1
<Rn>, <Rm>
-2
SMLAD
,
SMLADX
1
<Rn>, <Rm>
-2
SMUSD
,
SMUSDX
1
<Rn>, <Rm>
-2
SMLSD
,
SMLSDX
1
<Rn>, <Rm>
-2
SMMUL
,
SMMULR
2
<Rn>, <Rm>
-3
SMMLA
,
SMMLAR
2
<Rn>, <Rm> <Ra>
3
SMMLS
,
SMMLSR
2
<Rn>, <Rm> <Ra>
3