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Freescale Semiconductor MCF52211 Network Card User Manual

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Power Management

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

8-16 Freescale Semiconductor

I

2

C Module Enabled Yes

2

Enabled Yes

2

Stopped No

QSPI Enabled Yes

2

Enabled Yes

2

Stopped No

DMA Timers Enabled Yes

2

Enabled Yes

2

Stopped No

Interrupt Controller Enabled Yes

2

Enabled Yes

2

Enabled Yes

2

I/O Ports Enabled No Enabled No Enabled No

Reset Controller Enabled Yes

3

Enabled Yes

3

Enabled Yes

3

Chip Configuration Module Enabled No Enabled No Stopped No

Power Management Enabled No Enabled No Stopped No

Clock Module Enabled Yes

2

Enabled Yes

2

Enabled Yes

2

Edge port Enabled Yes

2

Enabled Yes

2

Stopped Yes

2

Programmable Interrupt Timers Enabled Yes

2

Program Yes

2

Stopped No

ADC Enabled Yes

2

Program Yes

2

Stopped No

General Purpose Timer Enabled Yes

2

Enabled Yes

2

Stopped No

PWM Program No Program No Stopped No

BDM Enabled Yes

4

Enabled Yes

4

Enabled Yes

4

JTAG Enabled No Enabled No Enabled No

1

Program Indicates that the peripheral function during the low-power mode is dependent on programmable bits in the

peripheral register map.

2

These modules can generate a interrupt that exits a low-power mode. The CPU begins to service the interrupt exception

after wakeup.

3

These modules can generate a reset that exits any low-power mode.

4

The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any low-power mode.

Upon exit from halt mode, the previous low-power mode is re-entered and changes made in halt mode remains in effect.

Table 8-10. CPU and Peripherals in Low-Power Modes (continued)

Module

Peripheral Status

1

/ Wakeup Capability

Wait Mode Doze Mode Stop Mode

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