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8051
Architectural Specification and Functional Description
T12
OSC
ALE
PORT 2
PORTO
Figure 2.41. Program Memory Read Cycle
Timing
ALE
CD
V
\0
V
RD
~0
0
PORT 2
X
ADDRESS A15-Aa
0 0
(6)
PORTO
INST
Irl
FLOAT
A7-Ao
I
FLOAT
>(
DATA
IN
I I I I I
Figure 2.42. Data Memory Read Cycle
Timing
ALE
G::
V
\
II
\0
®
PORT 2
X
ADDRESS A15-Aa
0
~
PORTO
INST
IN
I FLOAT
A7-Ao
D<
DATA
OUT
I
I I
I
I
NOTE: In Figures 2.42 and 2.43 the Prior and Subsequent Machine Cycles access Program Memory.
Figure 2.43. Data Memory Write Cycle Timing
27
FLOAT
I
CD
1/
®
I
FLOAT
I
II
@
II
0
ADD RESS
LOAT
ORF
ADD RESS
LOAT
OR
F
AFN-01488A-31