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8051 Single-Chip
Microcomputer
Architectural Specification
and
Functional Description
©Intel Corporation 1980. All rights reserved.
Contents
CHAPTER 1 INTRODUCTION
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.. .. .. .. .. ..
.... 1
1.0
Abstract. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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1
1.1
Intel's Complete Line
of
Single-Chip
Microcomputers
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1
1.2
Enhancing the 8048 Architecture for
the
80's
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1
CHAPTER 2 ARCHITECTURAL OVERVIEW AND
FUNCTIONAL DESCRIPTION
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2
2.0
The
8051
Family
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2
2.1
Macro-view
of
the
8051
Architecture
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2
2.1:
1
8051
CPU Architecture . . . . . . . . . . .
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2
2.1.2
On-Chip Peripheral Functions. . . . .
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3
2.1.2.1
Interrupt System
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. . . . . . . .
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3
2.1.2.2
I/O Facilities. . . . . . . . . . . . . .
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4
2.1.2.2.1
Open Drain I/O
Pins.
.
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4
2.1.2.2.2 Quasi-Bidirectional
I/O Pins
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4
2.1.2.2.3 Microprocessor Bus
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5
2.1.2.3 Timer/Event Counters
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6
2.1.2.4 Serial Communications. . . .
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7
2.2
CPU Hardware.
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9
2.2.1
Instruction
Decoder.
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9
2.2.2' Program
Counter
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9
2.2.3 Internal Data Memory
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9
2.2.3.1
Internal Data RAM
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9
2.2.3.2 Register Banks
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9
2.2.3.3 Special Function Registers
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9
2.2.3.4 A Register. . . . . . . . . . . . . . . .
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9
2.2.3.5 B Register. . . . . . . . . . . . . . . .
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9
2.2.3.6
PSW
Register.
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.. .. ..
....
9
2.2.3.7 Stack Pointer . . . . . . . . . . . . .
..
9
2.2.3.8 Data Pointer
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11
2.2.4 Arithmetic Section
.................
11
2.2.5
Program Control Section
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11
2.2.6
Oscillator and Timing Circuitry
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11
2.2.7 Boolean Processor
.................
11
2.3
Memory Organization
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11
2.4
Operand Addressing
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12
2.5
Data Manipulation
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"
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14
2.5.1
Data Transfer Operations
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14
2.5.2
logic
Operations
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15
2.5.3
Arithmetic Operations
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16
2.6
Control Transfer
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17
2.7
I nstruction Set
...........................
18
2.7.1
What the Instruction Set Is
...........
18
2.7.2 Organization
of
the Instruction Set
".
18
2.7.3 Operand Addressing Modes and
Associated Operations
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21
2.8
Interrupt System
........................
22
2.8.1
External Interrupts
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24
2.8.1.1
Transition-Activated
Interrupts
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24
2.8.1.2 level-Activated Interrupts
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24
2.9
Ports and I/O Pins
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24
AFN-Q1488A·03