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8051
Architectural Specification and Functional Description
TABLE 2-1
8051
INSTRUCTION
SET
SUMMARY
Notes
on
instruction set
and
addressing modes:
Rn
·~Register
R7-RO
of
the currently selected Register
Bani<.
data
-S-bit
internal
data
location's address. This could be an Inter-
nal
Data
RAM
location (0-127)
or
a
SFR
[i.e.
(:0
port. con-.
tTOI
register. status register. etc. (128-255)].
@Ri
-g-bit
Internal
Data
RAM
location (0-255) addressed indir-
IIdata
IIdata
16
ectly
through
register R I
or
RD.
-8-bit
constant included in instruction.
-16-bit
constant
included in instruction.
addrl6
-16-bit
destination address. Used by
LCALL
&
LJMP.
A
branch can
be anywhere within the 64K-byte Program Mem-
ory address space.
addrll
rei
-II-bit
destination address. Used by
ACALL
&
AJMP.
The
branch
will be within the same 2K-byte page
of
program
memory as the first byte
of
the following instruction.
·--Signed (two's complement) 8-bit offset byte. Used by
SJMP
and all
conditionaljumps.
Range is-128 to +
127
bytes relative
to first byte
of
the
following instruction.
bit
-Direct
Addressed bit in Internal
Data
RAM
or
Special Func-
tion Register.
*
- New operation
not
pTOvided
by
8048 i 8049.
Data
Tra
nafer
Oscillator
Mnemonic
Description
Bytes
Periods
MOV
A.Rn
Move· register
to
A
I
12
"MOV
A.data
Move direct byte
to
A
2
12
MOV A.@Ri
Move indirect
RAM
to
A
I
12
MOV A.lldata Move immediate
data
io
A
2
12
MOV Rn.A
Move A
to
register
I
12
"MOV
Rn.data
Move direct byte
to
register
2
24
MOV Rn.lldata Move immediate
data
to
2
12
register
"MOV
data.A
Move A
to
direct byte
2
12
"MOV
dala.Rn
Move register
10
direct byte
2
24
"MOV
data.data
Move direct byte
to
direct
3
24
byte
"MOV
data.@Ri
Move indirect
RAM
to
2
24
direct byte
"MOV
data.lldata
Move
immediate
data
to
3
24
direct byte
MOV@Ri.A
Move A
to
indirect
RAM
I
12
"MOV
@Ri.data
Move direct byte
to
2
24
indirect RAM
MOV @Ri,lIdata Move immediate
data
to
2
12
indirect
RAM
"MOV
DPTR.
Move l6-bit
constant
to
24
IIdata
16
Data
Pointer
"MOV
C,bit Move direct bit
to
carry
2
12
"MOV
bit.C
Move carry
to
direct bit
2
24
"MOVC
A.@A+ Move
Program
Memory
24
DPTR
byte addressed
by
A+DPTR
to
A
"MOVC
A.@A+PC
Move
Program
Memory
24
byte
addre"ed
by
A+PC
to
A
MOVX A.@Ri Move External Data
24
(8-bit address)
to
A
"MOVX
A.@DPTR
Move External
Data
24
(l6-bit
address) to A
MOVX @Ri.A Move A
to
External Data
24
(8-bit address)
·MOVX
@DPTR.A
Move A
to
External
Data
24
(l6-bit
address)
·PUSH
data
Move direct byte
to
staci<
2
24
and,inc.
SP
'POP
data
Move direct byte from
2
24
staci<
and
dec. S P
XCH
A.Rn
Exchange register with A
12
"XCH
A.data
Exchange direct byte
12
with A
XCH A.@Ri Exchange indirect
RAM
12
with A
XCHD
A.@Ri Exchange indirect RA
M',
12
least sig nibble with A's LSN
Interrupt Response Time: To finish execution
of
current instruction.
respond to the
interrupt
request. push the PC and
to
vector
to
the first
instruction
of
the
interrupt service progr.am requires
38
to
81
oscillator
periods
(3
to
71's
@
12
MHz).
INSTRUCTIONS
THAT
AFFECT
FLAG
SETTINGS'
INSTRUCTION
FLAG
INSTRVCTION
FLAG
C
OV AC
C
OV AC
ADD
X X X
CLR
C 0
ADDC
X
X X
CPL
C X
SUBB
X X X
ANL
C,bit X
'MUL
0 X
ANL
C:
bit X
DIV 0 X
ORL
C, bit X
DA X
ORL
C, bit
X
RRC
X
MOV C, 'bit
X
RLC
X
CJNE
X
SETB
C
'Note
that operations
on
SFR
byte address
20X
or
bit addresses 209-215
(i.e.
the
PSW
or
bits in the PSW) will also affect nag settings.
Logic
Oscillator
Mnemonic
Description
Bytes
Periods
ANL
A.Rn
AND
register
to
A I
12
"ANL
A.data
AND
direct byte
to
A 2
12
ANL
A.@Ri
AND
indirect
RAM
to A I
12
ANL
A.lldata
AND
immediate
data
to
A 2
12
"ANL
data.A
AND
A to direct byte 2
12
"ANL
data.lldata
AND
immediate
data
to
3
24
direct byte
"ANL
C,bit
AND
direct bit
to
carry
2
24
'ANL
C,bit
...
ND
complement
of
2
24
direct bit
to
carry
ORL
A.Rn
OR
register
to
A I
12
"ORL
A.data
OR
direct byte to A
2
12
ORL
A.@Ri
OR
indirect RAM
to
A
I
12
ORL
A.lldata
OR
immediate
data
to
A
2
12
"ORL
data.A
OR
A to direct byte
2
12
'ORL
data.lldata
OR
immediate
data
to
3
24
direct byte
"ORL
C,bit
OR
direct bit
to
carry
24
"ORL
C, bit
OR
complement
of
direct
24
bit to carry
XRL
A.Rn
Exclusive-OR register to A
12
"XRL
A.data
Exclusive-OR direct byte
12
to A
XRL
A.@Ri Exclusive-OR indirect
12
RAM
to
A
XRL
A.lldata
Exclusive-OR
immediate
12
data
to A
'XRL
data.A
Exclusive-OR A
to
direct
2
12
byte
"XRL
data.lldata Exclusive-OR immediate
24
data
to direct byte
·SETB
C Set carry 1
12
"SETB
bit Set direct bit 2
12
CLR
A Clear A
12
CLR
c.:
Clear carry
12
·CLR
bit Clear direct bit
2
12
CPL
A
Complement A
12
CPL
C
Complement carry
12
"CPL
bit Complement direct bit
12
RL A
Rotate A Left
12
RLC
A Rotate A Left through
12
carry
RR A
Rotate A Right
12
RRC
A Rotate A Right
through
12
carry
SWAP
A Rotate A left four
12
(exchange nibbles within
A)
All
mnemonics
copyrighted©
Intel
Corporation
1980.
AFN-01488A-41
37