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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
µ
PD78054 Subseries)
(a) Bus release signal (REL)
The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the
high level when the SCK0 line is at the high level (without serial clock output).
This signal is output by the master device.
Figure 16-12. Bus Release Signal
Caution A transition of the SB0 (SB1) pin from low to high while the SCK0 line is high is
interpreted as a bus release signal. Therefore, a shift in the change timing of the bus
due to the influence of the board capacitance, etc., may be incorrectly identified as a
bus release signal, regardless of whether data is being transmitted. For this reason,
special care must be taken regarding wiring.
The bus release signal indicates that the master device is going to transmit an address to the slave device.
The slave device incorporates hardware to detect the bus release signal.
(b) Command signal (CMD)
The command signal is a signal with the SB0 (SB1) line which has changed from the high level to the
low level when the SCK0 line is at the high level (without serial clock output). This signal is output by
the master device.
Figure 16-13. Command Signal
A command signal indicates that the master is to transmit a command to a slave (however, the command
signal following a bus release signal indicates that the master is to transmit an address).
The slave device incorporates hardware to detect the command signal.
Caution A transition of the SB0 (SB1) pin from low to high while the SCK0 line is high is
interpreted as a command signal. Therefore, a shift in the change timing of the bus due
to the influence of the board capacitance, etc., may be incorrectly identified as a
command signal, regardless of whether data is being transmitted. For this reason,
special care must be taken regarding wiring.
SCK0
"H"
SB0 (SB1)
SCK0
"H"
SB0 (SB1)