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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
µ
PD78054Y Subseries)
(2) Slave wait release (slave transmission)
Slave wait status is released by WREL flag (bit 2 of interrupt timing specify register (SINT)) setting or
execution of an serial I/O shift register 0 (SIO0) write instruction.
If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the
clock rises without the start transmission bit being output in the data line. Therefore, as shown in Figure 17-
25, data should be transmitted by manipulating the P27 output latch through the program. At this time,
control the low-level width ("a" in Figure 17-25) of the first serial clock at the timing used for setting the P27
output latch to 1 after execution of an SIO0 write instruction.
In addition, if the acknowledge signal from the master is not output (if data transmission from the slave is
completed), set 1 in the WREL flag of SINT and release the wait.
For these timings, see Figure 17-23.
Figure 17-25. Slave Wait Release (Transmission)
Writing
FFH
to SIO0
Setting
CSIIF0
Setting
ACKD
Serial reception
9
a
23
A0 R ACK D7 D6 D5
P27
output
latch 1
Setting
CSIIF0
ACK
output
Serial transmission
Write
data
to SIO0
P27
output
latch 0
Wait
release
Software operation
Hardware operation
SCL
Software operation
Hardware operation
Transfer line
Master device operation
Slave device operation
1
SDA0(SDA1)