Filter
Top Products
564
CHAPTER 27 INSTRUCTION SET
27.2 Operation List
Clock Flag
Note 1 Note 2
ZACCY
r, #byte 2 4 – r ← byte
saddr, #byte 3 6 7 (saddr) ← byte
sfr, #byte 3 – 7 sfr ← byte
A, r
Note 3
12 –A ← r
r, A
Note 3
12 –r ← A
A, saddr 2 4 5 A ← (saddr)
saddr, A 2 4 5 (saddr) ← A
A, sfr 2 – 5 A ← sfr
sfr, A 2 – 5 sfr ← A
A, !addr16 3 8 9 + n A ← (addr16)
!addr16, A 3 8 9 + m (addr16) ← A
PSW, #byte 3 – 7 PSW ← byte ×××
A, PSW 2 – 5 A ← PSW
PSW, A 2 – 5 PSW ← A ×××
A, [DE] 1 4 5 + n A ← (DE)
[DE], A 1 4 5 + m (DE) ← A
A, [HL] 1 4 5 + n A ← (HL)
[HL], A 1 4 5 + m (HL) ← A
A, [HL + byte] 2 8 9 + n A ← (HL + byte)
[HL + byte], A 2 8 9 + m (HL + byte) ← A
A, [HL + B] 1 6 7 + n A ← (HL + B)
[HL + B], A 1 6 7 + m (HL + B) ← A
A, [HL + C] 1 6 7 + n A ← (HL + C)
[HL + C], A 1 6 7 + m (HL + C) ← A
A, r
Note 3
12 –A ↔ r
A, saddr 2 4 6 A ↔ (saddr)
A, sfr 2 – 6 A ↔ sfr
A, !addr16 3 8
10 + n + m
A ↔ (addr16)
XCH A, [DE] 1 4
6 + n + m
A ↔ (DE)
A, [HL] 1 4
6 + n + m
A ↔ (HL)
A, [HL + byte] 2 8
10 + n + m
A ↔ (HL + byte)
A, [HL + B] 2 8
10 + n + m
A ↔ (HL + B)
A, [HL + C] 2 8
10 + n + m
A ↔ (HL + C)
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.
2. When an area except the internal high-speed RAM area is accessed.
3. Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
CPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
Mnemonic Operands Byte Operation
Instruction
Group
MOV
8-bit data
transfer