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62-11
Software Configuration Guide—Release 15.0(2)SG
OL-23818-01
Chapter 62 Performing Diagnostics
• WS-C4948G-10GE
• ME-4924-10GE
• WS-X45-SUP6-E
• WS-X45-SUP6L-E
The POST results are indicated with a period (.) or a Pass for Pass, an F for a Fail and a U for Untested.
POST Result Example
For all the supervisor engines, POST performs CPU, traffic, system, system memory, and feature tests.
For CPU tests, POST verifies appropriate activity of the supervisor engine SEEPROM, temperature
sensor, and Ethernet end-of-band channel (EOBC), when used.
The following example illustrates the output of a CPU subsystem test on all supervisor engines except
the WS-X4013+TS:
[..]
Cpu Subsystem Tests ...
seeprom: . temperature_sensor: . eobc: .
[..]
The following example illustrates the output of a CPU subsystem test on a WS-X4013+TS supervisor
engine:
[..]
Cpu Subsystem Tests ...
seeprom: . temperature_sensor: .
[..]
For traffic tests, the POST sends packets from the CPU to the switch. These packets loop several times
within the switch core and validate the switching, the Layer 2 and the Layer 3 functionality. To isolate
the hardware failures accurately, the loop back is done both inside and outside the switch ports.
The following example illustrates the output of a Layer 2 traffic test at the switch ports on the supervisor
engines WS-X4516, WS-X4516-10GE, WS-X4013+10GE, WS-C4948G-10GE:
Port Traffic: L2 Serdes Loopback ...
0: . 1: . 2: . 3: . 4: . 5: . 6: . 7: . 8: . 9: . 10: . 11: .
12: . 13: . 14: . 15: . 16: . 17: . 18: . 19: . 20: . 21: . 22: . 23: .
24: . 25: . 26: . 27: . 28: . 29: . 30: . 31: . 32: . 33: . 34: . 35: .
36: . 37: . 38: . 39: . 40: . 41: . 42: . 43: . 44: . 45: . 46: . 47: .
The following example illustrates the output of a Layer 2 traffic test at the switch ports on the supervisor
engines WS-X4013+TS, WS-X4515, WS-X4013+, WS-X4014, WS-C4948G:
Port Traffic: L2 Serdes Loopback ...
0: . 1: . 2: . 3: . 4: . 5: . 6: . 7: . 8: . 9: . 10: . 11: .
12: . 13: . 14: . 15: . 16: . 17: . 18: . 19: . 20: . 21: . 22: . 23: .
24: . 25: . 26: . 27: . 28: . 29: . 30: . 31:
POST also performs tests on the packet and system memory of the switch. These are numbered
dynamically in ascending order starting with 1 and represent different memories.