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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Programming Model
Page 114 of 377
gx_02.fm.(1.2)
March 27, 2006
Table 2-36 shows the mftb instruction.
Simplified mnemonics are provided for the mftb instruction so it can be coded with the TBR name as part of
the mnemonic rather than requiring it to be coded as an operand. See Appendix F, “Simplified Mnemonics” in
the PowerPC Microprocessor Family: The Programming Environments Manual for simplified mnemonic
examples and for simplified mnemonics for Move-from Time Base (mftb) and Move-from Time Base Upper
(mftbu), which are variants of the mftb instruction rather than of mfspr. The mftb instruction serves as both
a basic and simplified mnemonic. Assemblers recognize an mftb mnemonic with two operands as the basic
form, and an mftb mnemonic with one operand as the simplified form. Note that the 750GX ignores the
extended opcode differences between mftb and mfspr by ignoring bit 25 and treating both instructions iden-
tically.
Implementation Notes: The following information relates to using the time-base implementation in the
750GX:
• The 750GX allows user-mode read access to the time-base counter through the use of the Move-from
Time Base (mftb) and the Move-from Time Base Upper (mftbu) instructions. As a 32-bit PowerPC imple-
mentation, the 750GX can access TBU and TBL only separately, whereas 64-bit implementations can
access the entire TB Register at once.
• The time-base counter is clocked at a frequency that is one-fourth that of the bus clock.
2.3.5.2 Memory Synchronization Instructions—VEA
Memory synchronization instructions control the order in which memory operations are completed with
respect to asynchronous events, and the order in which memory operations are seen by other processors or
memory-access mechanisms. See Chapter 3, Instruction-Cache and Data-Cache Operation, on page 121 for
more information about these instructions and about related aspects of memory synchronization.
In addition to the sync instruction (specified by UISA), the VEA defines the Enforce In-Order Execution of I/O
(eieio) and Instruction Synchronize (isync) instructions. The number of cycles required to complete an eieio
instruction depends on system parameters and on the processor's state when the instruction is issued. As a
result, frequent use of this instruction might degrade performance slightly.
Table 2-37 describes the memory synchronization instructions defined by the VEA.
Table 2-36. Move-from Time Base Instruction
Name Mnemonic Syntax
Move-from Time Base mftb rD, TBR