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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_08.fm.(1.2)
March 27, 2006
Bus Interface Operation
Page 279 of 377
8. Bus Interface Operation
This chapter describes the PowerPC 750GX microprocessor’s bus interface and its operation. It shows how
the 750GX signals, defined in Chapter 7, Signal Descriptions, on page 249, interact to perform address and
data transfers.
The bus interface buffers bus requests from the instruction and data caches, and executes the requests per
the 60x bus protocol. It includes Address Register queues, prioritizing logic, and bus control logic. It captures
snoop addresses for snooping in the cache and in the Address Register queues. It also snoops for reserva-
tions and holds the touch load address for the cache. All data storage for the Address Register buffers (load-
and-store data buffers) are located in the cache section. The data buffers are considered temporary storage
for the cache and not part of the bus interface.
The general functions and features of the bus interface are:
• Eight Address Register buffers that include the following:
– Instruction-cache load address buffer
– Four data-cache load address buffers
– Two data-cache castout/store address buffers
– Data-cache snoop copy-back address buffer (associated data block buffer located in cache)
– Reservation address buffer for snoop monitoring
– L2 castout buffer
• Pipeline collision detection for data-cache buffers
• Reservation address snooping for Load Word and Reserve Indexed (lwarx) and Store Word Conditional
Indexed (stwcx.) instructions
• Address pipelining for four load/store transactions and one snoop transaction
• Load ahead of store capability
Figure 8-1 on page 280 provides a conceptual block diagram of the bus interface. The Address Register
queues in the figure hold transaction requests that the bus interface can issue on the bus independently of
the other requests. The bus interface can have up to four load/store transactions operating on the bus at any
given time through the use of address pipelining. Enabling MuM allows four cache reloads or cache inhibited
loads to be pipelined in a continuous fashion on the 60x bus. If there is a miss in the L2 cache, then the
request is passed on to the BIU via three additional L2-to-BIU reload-request queues. Data returned from the
bus is loaded into the data-cache reload buffer, one of the L2 reload buffers, and the critical word is forwarded
to the load/store unit. For a D-cache-line load due to the cache miss of a load instruction, the critical double
word is simultaneously written to the 256-bit line fill buffer and forwarded to the requesting load/store unit.