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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_01.fm.(1.2)
March 27,2006
PowerPC 750GX Overview
Page 45 of 377
1.5 Instruction Set
All PowerPC instructions are encoded as single-word (32-bit) instructions. Instruction formats are consistent
among all instruction types (the primary operation code is always 6 bits, register operands are always speci-
fied in the same bit fields in the instruction), permitting efficient decoding to occur in parallel with operand
accesses. This fixed instruction length and consistent format greatly simplify instruction pipelining.
For more information, see Chapter 2, Programming Model, on page 57.
1.5.1 PowerPC Instruction Set
The PowerPC instructions are divided into the following categories.
• Integer instructions—These include computational and logical instructions.
– Integer arithmetic instructions
– Integer compare instructions
– Integer logical instructions
– Integer rotate and shift instructions
• Floating-point instructions—These include floating-point computational instructions, as well as instruc-
tions that affect the FPSCR.
– Floating-point arithmetic instructions
– Floating-point multiply/add instructions
– Floating-point rounding and conversion instructions
– Floating-point compare instructions
– Floating-point status and control instructions
• Load/store instructions—These include integer and floating-point load-and-store instructions.
– Integer load-and-store instructions
– Integer load-and-store multiple instructions
– Floating-point load and store
– Primitives used to construct atomic memory operations (Load Word and Reserve Indexed [lwarx]
and Store Word Conditional Indexed [stwcx.] instructions)
• Flow-control instructions—These include branching instructions, Condition Register logical instructions,
trap instructions, and other instructions that affect the instruction flow.
– Branch and trap instructions
– Condition Register logical instructions (sets conditions for branches)
– System call
• Processor control instructions—These instructions are used to synchronize memory accesses and to
manage caches, TLBs, and the Segment Registers.
– Move-to/Move-from SPR instructions
– Move-to/Move-from MSR
– Synchronize (processor and memory system)
– Instruction synchronize
– Order loads and stores
• Memory control instructions—To provide control of caches, TLBs, and SRs.
– Supervisor-level cache-management instructions
– User-level cache instructions
– Segment Register manipulation instructions