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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
L2 Cache
Page 328 of 377
gx_09.fm.(1.2)
March 27, 2006
The execution of the Store Word Conditional Indexed (stwcx.) instruction results in single-beat writes from
the L1 data cache. These single-beat writes are processed by the L2 cache according to hit/miss status, L1
and L2 write-through configuration, and reservation-active status. If the address associated with the stwcx.
instruction misses in the L2 cache, or if the reservation is no longer active, the stwcx. instruction bypasses
the L2 cache and is forwarded to the 60x bus interface. If the stwcx. instruction hits in the L2 cache and the
reservation is still active, one of the following actions occurs:
• If the stwcx. hits a modified sector in the L2 cache (independent of write-through status), or if the stwcx.
hits both the L1 and L2 caches in copy-back mode, the stwcx. is written to the L2 cache and the reserva-
tion completes.
• If the stwcx. hits an unmodified sector in the L2 cache, and either the L1 or L2 cache is in write-through
mode, the stwcx. is forwarded to the 60x bus interface and the sector hit in the L2 cache is invalidated.
L1 cache-block-push operations generated by the execution of Data Cache Block Flush (dcbf) and Data
Cache Block Store (dcbst) instructions write through to the 60x bus interface and invalidate the L2-cache
sector if they hit. The execution of dcbf and dcbst instructions that do not cause a cache-block-push from the
L1 cache are forwarded to the L2 cache to perform a sector invalidation and/or a push from the L2 cache to
the 60x bus as required. If the dcbf and dcbst instructions do not cause a sector push from the L2 cache,
they are forwarded to the 60x bus interface for address-only broadcast if HID0[ABE] is set to 1.
The L2 flush mechanism is similar to the L1 data-cache flush mechanism. The L2 flush requires that the
entire L1 data cache be flushed prior to flushing the L2 cache. Also, interrupts must be disabled during the L2
flush so that the LRU algorithm does not get disturbed. The L2 can be flushed by executing uniquely
addressed load instructions to each of the 32-byte blocks of the L2 cache. This requires a load to each of the
two sectors in each of the four ways in each of the 4096 sets of the L2 cache. The loads must not hit in the L1
cache in order to effect a flush of the L2 cache.
The Data Cache Block Invalidate (dcbi) instruction is always forwarded to the L2 cache and causes a sector
invalidation if a hit occurs. The instruction is also forwarded to the 60x bus interface for broadcast if
HID0[ABE] is set to 1. The instruction-cache-block invalidate (icbi) instruction invalidates only L1-cache
blocks and is never forwarded to the L2 cache.
Any Data Cache Block Set To Zero (dcbz) instructions that are marked global do not affect the L2 cache
state. If an instruction hits in the L1 and L2 caches, the L1 data-cache block is cleared and the instruction
completes. If an instruction misses in the L2 cache, it is forwarded to the 60x bus interface for broadcast. Any
dcbz instructions that are marked nonglobal act only on the L1 data cache without reference to the state of
the L2 cache.
The Synchronize (sync) and Enforce In-Order Execution of I/O (eieio) instructions bypass the L2 cache and
are forwarded to the 60x bus.