Filter
Top Products
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_10.fm.(1.2)
March 27, 2006
Power and Thermal Management
Page 341 of 377
Note: If the PLL software configuration is used, sufficient time must be allowed for the chosen PLL to lock.
See the PowerPC 750GX RISC Microprocessor Datasheet for more information.
The following sequence can be used to change processor clock frequency. Assume PLL0 is currently the
source for the processor clock. The first step is to configure PLL1 to produce the desired clock frequency, by
setting HID1[PR1] and HID1[PC1] to the appropriate values. Next, wait for PLL1 to lock. The lock time is the
same for both PLLs and is provided in the PowerPC 750GX RISC Microprocessor Datasheet. Finally, set
HID1[PS] to a 1 to initiate the transition from PLL0 to PLL1 as the source of the processor clocks. From the
time the HID1 Register is updated to select the new PLL, the transition to the new clock frequency will
complete within three bus cycles. After the transition, the HID1(PSTAT1) bit indicates which PLL is in use.
Once both PLLs are running and locked, the processor frequency can be toggled with very low latency. For
instance, when it is time to change back to the PLL0 frequency, there is no need to wait for PLL lock.
HID1[PS] can be reset to 0, causing the processor clock source to transition from PLL1 back to PLL0. If PLL0
will not be needed for some time, it can be configured to be off while not in use. This is done by resetting the
HID1[PC0] field to 0, and setting HID1[PI0] to 1. Turning the nonselected PLL off results in a modest power
savings, but introduces added latency when changing frequency. If PLL0 is configured to be off, the proce-
dure for switching to PLL0 as the selected PLL involves changing the configuration and range bits, waiting for
lock, and then selecting PLL0, as described in the previous paragraph.
The following are hazards that must be avoided in reconfiguring the PLLs:
• The configuration and range bits in HID1 should only be modified for the nonselected PLL, since it will
require time to lock before it can be used as the source for the processor clock.
• The HID1[PI0] bit should only be modified when PLL0 is not selected.
• Whenever one of the PLLs is reconfigured, it must not be selected as the active PLL until enough time
has elapsed for the PLL to lock.
• At all times, the frequency of the processor clock, as determined by the various configuration settings,
must be within the specification range for the current operating conditions. In particular, in systems where
V
DD
can be varied to achieve additional power efficiency, a transition from low frequency to high fre-
quency requires that V
DD
is at a sufficiently high level to support the higher frequency.
• Never select a PLL that is in the “off” configuration.
10.3.2 Configuration Restriction on Frequency Transitions
It is considered a programming error to switch from one PLL to the other when both are configured in a half-
cycle multiplier mode. For example, with PLL0 configured in 9:2 mode (PLL_CFG[0:4] = '01001') and PLL1
configured in 13:2 mode (PLL_CFG[0:4] = '01101'), changing the select bit (HID1[PS]) is not allowed. In
cases where such a pairing of configurations is desired, an intermediate full-cycle configuration must be used
between the two half-cycle modes. For example, with PLL0 at 9:2, PLL1 configured at 6:1 is selected. Then
PLL0 is reconfigured at 13:2, locked, and selected. For more information about hardware-implementation-
dependent bit functions for HID1, see Section 2.1.2.3 on page 70.