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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_08.fm.(1.2)
March 27, 2006
Bus Interface Operation
Page 321 of 377
Note that although the 750GX can pipeline any write transaction behind the read transaction, special care
should be used when using the enveloped write feature. It is envisioned that most system implementations
will not need this capability; for these applications, DBWO
should remain negated. In systems where this
capability is needed, DBWO
should be asserted under the following scenario:
1. The 750GX initiates a read transaction (either single-beat or burst) by completing the read address ten-
ure with no address retry.
2. Then, the 750GX initiates a write transaction by completing the write address tenure, with no address
retry.
3. At this point, if DBWO
is asserted with a qualified data-bus grant to the 750GX, the 750GX asserts DBB
and drives the write data onto the data bus, out of order with respect to the address pipeline. The write
transaction concludes with the 750GX negating DBB
.
4. The next qualified data-bus grant signals the 750GX to complete the outstanding read transaction by
latching the data on the bus. This assertion of DBG
should not be accompanied by an asserted DBWO.
Any number of bus transactions by other bus masters can be attempted between any of these steps.
Note the following regarding DBWO
:
•DBWO
can be asserted if no data-bus read is pending, but it has no effect on write ordering.
• The ordering and presence of data-bus writes is determined by the writes in the write queues at the time
BG
is asserted for the write address (not DBG). If a particular write is desired (for example, a cache-line-
snoop-push-out operation), then BG
must be asserted after that particular write is in the queue, and it
must be the highest priority write in the queue at that time. A cache-line-snoop-push-out operation might
be the highest priority write, but more than one might be queued.
• Because more than one write might be in the write queue when DBG
is asserted for the write address,
more than one data-bus write can be enveloped by a pending data-bus read.
The arbiter must monitor bus operations and coordinate the various masters and slaves with respect to the
use of the data bus when DBWO
is used. Individual DBG signals associated with each bus device should
allow the arbiter to synchronize both pipelined and split-transaction bus organizations. Individual DBG
and
DBWO
signals provide a primitive form of source-level tagging for the granting of the data bus.
Note that use of the DBWO
signal allows some operation-level tagging with respect to the 750GX and the use
of the data bus.