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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Memory Management
Page 196 of 377
gx_05.fm.(1.2)
March 27, 2006
For information on the synchronization requirements for changes to MSR[IR] and MSR[DR], see
Section 2.3.2.4, Synchronization, on page 90 in this manual and “Synchronization Requirements for Special
Registers and for Lookaside Buffers” in Chapter 2 of the PowerPC Microprocessor Family: The Programming
Environments Manual.
5.3 Block-Address Translation
The block-address-translation (BAT) mechanism in the OEA provides a way to map ranges of effective
addresses larger than a single page into contiguous areas of physical memory. Such areas can be used for
data that is not subject to normal virtual memory handling (paging), such as a memory-mapped display buffer
or an extremely large array of numerical data.
Block-address translation in the 750GX is described in Chapter 7, “Memory Management,” in the PowerPC
Microprocessor Family: The Programming Environments Manual for 32-bit implementations.
Implementation Note: The 750GX’s BAT registers are not initialized by the hardware after the power-up or
reset sequence. Consequently, all valid bits in both instruction and data BATs must be cleared before setting
any BAT for the first time. This is true regardless of whether address translation is enabled. Also, software
must avoid overlapping blocks while updating a BAT or areas. Even if translation is disabled, multiple BAT
hits are treated as programming errors and can corrupt the BAT registers and produce unpredictable results.
Always reset to zero during the reset Interrupt Service Routine (ISR). After zeroing all BATs, set them (in
order) to the desired values. A hard reset (HRESET
) disorders the BATs. A soft reset (SRESET) does not.
5.4 Memory Segment Model
The 750GX adheres to the memory segment model as defined in Chapter 7, “Memory Management,” in the
PowerPC Microprocessor Family: The Programming Environments Manual for 32-bit implementations.
Memory in the PowerPC OEA is divided into 256-MB segments. This segmented memory model provides a
way to map 4-KB pages of effective addresses to 4-KB pages in physical memory (page-address translation),
while providing the programming flexibility afforded by a large virtual address space (52 bits).
The segment/page-address-translation mechanism might be superseded by the block-address-translation
(BAT) mechanism described in Section 5.3, Block-Address Translation, on page 196. If not, the translation
proceeds in the following two steps:
1. From effective address to the virtual address (which never exists as a specific entity but can be consid-
ered to be the concatenation of the virtual page number and the byte offset within a page), and
2. From virtual address to physical address.
This section highlights those areas of the memory segment model defined by the OEA that are specific to the
750GX.
5.4.1 Page History Recording
Referenced (R) and changed (C) bits in each PTE keep history information about the page. They are main-
tained by a combination of the 750GX’s table-search hardware and the system software. The operating
system uses this information to determine which areas of memory to write back to disk when new pages must
be allocated in main memory. Referenced and changed recording is performed only for accesses made with