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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Instruction Timing
Page 240 of 377
gx_06.fm.(1.2)
March 27, 2006
Table 6-6 lists condition register logical instruction latencies.
Table 6-7 shows integer instruction latencies. Note that the IU1 executes all integer arithmetic instructions—
multiply, divide, shift, rotate, add, subtract, and compare. The IU2 executes all integer instructions except
multiply and divide (shift, rotate, add, subtract, and compare).
Table 6-6. Condition Register Logical Instructions
Instruction Mnemonic
Primary
Opcode
Extended
Opcode
Unit Cycles Serialization
Condition Register AND crand 19 257 SRU 1 Execution
Condition Register AND
with Complement
crandc 19 129 SRU 1 Execution
Condition Register
Equivalent
creqv 19 289 SRU 1 Execution
Condition Register
NAND
crnand 19 225 SRU 1 Execution
Condition Register NOR crnor 19 33 SRU 1 Execution
Condition Register OR cror 19 449 SRU 1 Execution
Condition Register OR
with Complement
crorc 19 417 SRU 1 Execution
Condition Register XOR crxor 19 193 SRU 1 Execution
Move Condition
Register Field
mcrf 19 0 SRU 1 Execution
Move to Condition
Register from XER
mcrxr 31 512 SRU 1 Execution
Move From Condition
Register
mfcr 31 19 SRU 1 Execution
Move To Condition
Register Fields
mtcrf 31 144 SRU 1 Execution
Table 6-7. Integer Instructions (Page 1 of 3)
Instruction Mnemonic
Primary
Opcode
Extended
Opcode
Unit Cycles Serialization
Add Carrying addc[o][.] 31 10 IU1/IU2 1 —
Add Extended adde[o][.] 31 138 IU1/IU2 1 Execution
Add Immediate addi 14 — IU1/IU2 1 —
Add Immediate Carrying addic 12 — IU1/IU2 1 —
Add Immediate Carrying
and Record
addic. 13 — IU1/IU2 1 —
Add Immediate Shifted addis 15 — IU1/IU2 1 —
Add to Minus One
Extended
addme[o][.] 31 234 IU1/IU2 1 Execution
Add to Zero Extended addze[o][.] 31 202 IU1/IU2 1 Execution
Add add[o][.] 31 266 IU1/IU2 1 —
AND with Complement andc[.]31 60IU1/IU21—
AND Immediate andi. 28 — IU1/IU2 1 —