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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Performance Monitor and System Related Features
Page 352 of 377
gx_11.fm.(1.2)
March 27, 2006
Software is expected to use the mtspr instruction to explicitly set PMC to nonoverflowed values. Setting an
overflowed value might cause an erroneous exception. For example, if both MMCR0[ENINT] and either
PMC1INTCONTROL or PMCINTCONTROL are set and the mtspr instruction loads an overflow value, an
interrupt signal might be generated without event counting having taken place.
The event to be monitored can be chosen by setting MMCR0[19:31]. The selected events are counted begin-
ning when MMCR0 is set until either MMCR0 is reset or a performance-monitor interrupt is generated.
Table 11-2 lists the selectable events and their encodings.
Bits MMCR0[26:31] specify events associated with PMC2, as shown in Table 11-3.
Table 11-2. PMC1 Events—MMCR0[19:25] Select Encodings
Encoding Description
000 0000 Register holds current value.
000 0001 Number of processor cycles.
000 0010 Number of instructions that have completed. Does not include folded branches.
0000011
Number of transitions from 0 to 1 of specified bits in the Time Base Lower (TBL) register. Bits are specified through
RTCSELECT, MMCR0[7–8].
00 31
01 23
10 19
11 15
0000100 Number of instructions dispatched—0, 1, or 2 instructions per cycle.
0000101 Number of Enforce In-Order Execution of I/O (eieio) instructions completed.
0000110 Number of cycles spent performing table-search operations for the instruction translation lookaside buffer (ITLB).
0000111
Number of accesses that hit the L2. This event includes cache operations (such as data-cache-block set-to-zero
[dcbz]).
0001000 Number of valid instruction effective addresses (EAs) delivered to the memory subsystem.
0001001
Number of times the address of an instruction being completed matches the address in the Instruction Address
Breakpoint Register (IABR).
0001010 Number of loads that miss the L1 with latencies that exceeded the threshold value.
0001011 Number of branches that are unresolved when processed.
0001100 Number of cycles the dispatcher stalls due to a second unresolved branch in the instruction stream.
All others Reserved. Might be used in a later revision.
Table 11-3. PMC2 Events—MMCR0[26:31] Select Encodings (Page 1 of 2)
Encoding Description
00 0000 Register holds current value.
00 0001 Counts processor cycle.
00 0010 Counts completed instructions. Does not include folded branches.
00 0011
Counts transitions from 0 to 1 of TBL bits specified through MMRC0[RTCSELECT].
00 47
01 51
10 55
11 63
00 0100 Counts instructions dispatched: 0, 1, or 2 instructions per cycle.