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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_05.fm.(1.2)
March 27, 2006
Memory Management
Page 201 of 377
To uniquely identify a TLB entry as the required PTE, each TLB entry contains, in addition to the PTE, an
additional 4-bit field called the Extended Page Index (EPI). The EPI contains bits 10–13 of the EA. Software
cannot access the TLB arrays directly, except to invalidate an entry with the tlbie instruction.
Each set of TLB entries has one associated LRU bit. The LRU bit for a set is updated any time either entry is
used, even if the access is speculative. Invalid entries are always the first to be replaced.
Although both MMUs can be accessed simultaneously (both sets of Segment Registers and TLBs can be
accessed in the same clock), only one exception condition can be reported at a time. ITLB miss exception
conditions are reported when there are no more instructions to be dispatched or retired (the pipeline is
empty), and DTLB miss exception conditions are reported when the load or store instruction is ready to be
retired. See Chapter 6, Instruction Timing, on page 209 for more detailed information about the internal pipe-
lines and the reporting of exceptions.
When an instruction or data access occurs, the effective address is routed to the appropriate MMU. EA0–EA3
select one of the 16 Segment Registers and the remaining effective address bits, and the virtual segment ID
(VSID) field from the Segment Register is passed to the TLB. EA[14–19] then select two entries in the TLB.
The valid bits are checked and the 40-bit virtual page number (24-bit VSID and EA[4–19]) must match the
VSID, EPI, and API fields of the TLB entries. If one of the entries hits, the page-protection (PP) bits are
checked for a protection violation. If these bits do not cause an exception, the C bit is checked and a table-
search operation is initiated if C must be updated. If C does not require updating, the real page number (RPN)
value is passed to the memory subsystem and the WIMG bits are then used as attributes for the access.
Although address translation is disabled on a reset condition, the valid bits of TLB entries are not automati-
cally cleared. Thus, TLB entries must be explicitly cleared by the system software (with the tlbie instruction)
before the valid entries are loaded and address translation is enabled. Also, note that the Segment Registers
do not have a valid bit, and so they should also be initialized before translation is enabled.
5.4.3.2 TLB Invalidation
The
750GX implements the optional tlbie and tlbsync instructions, which are used to invalidate TLB entries.
The execution of the tlbie instruction always invalidates four entries—both the ITLB and DTLB entries
indexed by EA[14–19].
The architecture allows tlbie to optionally enable a TLB invalidate signaling mechanism in hardware so that
other processors also invalidate their resident copies of the matching PTE. The 750GX does not signal the
TLB invalidation to other processors, nor does it perform any action when a TLB invalidation is performed by
another processor.
The tlbsync instruction causes instruction execution to stop if the TLBISYNC
signal is asserted. If TLBISYNC
is negated, instruction execution might continue or resume after the completion of a tlbsync instruction.
Section 8.7.2, TLBISYNC Input, on page 319 describes the TLB synchronization mechanism in further detail.
The tlbia instruction is not implemented on the 750GX
, and when its opcode is encountered, an illegal
instruction program exception is generated. To invalidate all entries of both TLBs, 64 tlbie instructions must
be executed, incrementing the value in EA14–EA19 by one each time. (See Chapter 8, “Instruction Set” in the
the PowerPC Microprocessor Family: The Programming Environments Manual for detailed information about
this instruction.) Software must ensure that instruction fetches or memory references to the virtual pages
specified by the tlbie have been completed prior to executing the tlbie instruction.