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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_11.fm.(1.2)
March 27, 2006
Performance Monitor and System Related Features
Page 349 of 377
11. Performance Monitor and System Related Features
The performance-monitor facility provides the ability to monitor and count predefined events such as
processor clocks, misses in the instruction cache, data cache, or L2 cache, types of instructions dispatched,
mispredicted branches, and other occurrences. The count of such events (which might be an approximation)
can be used to trigger the performance-monitor exception. The performance-monitor facility is not defined by
the PowerPC Architecture.
The performance monitor can be used for the following:
• To increase system performance with efficient software, especially in a multiprocessing system. Memory
hierarchy behavior can be monitored and studied in order to develop algorithms that schedule tasks (and
perhaps partition them) and that structure and distribute data optimally.
• To improve processor architecture, the detailed behavior of the PowerPC 750GX’s structure must be
known and understood in many software environments. Some environments might not be easily charac-
terized by a benchmark or trace.
• To help system developers bring up, debug, and tune their systems.
The performance monitor uses the following 750GX-specific Special-Purpose Registers (SPRs).
• The Performance-Monitor Counter Registers (PMC1–PMC4) are used to record the number of times a
certain event has occurred. UPMC1–UPMC4 provide user-level read access to these registers.
• The Monitor Mode Control Registers (MMCR0–MMCR1) are used to enable various performance-moni-
tor interrupt functions and select events to count. UMMCR0–UMMCR1 provide user-level read access to
these registers.
• The Sampled Instruction Address Register (SIA) contains the effective address of an instruction execut-
ing at or around the time that the processor signals the performance-monitor interrupt condition. USIA
provides user-level read access to the SIA.
Four 32-bit counters in the 750GX count occurrences of software-selectable events. Two control registers,
MMCR0 and MMCR1, are used to control performance-monitor operation. The counters and the Control
Registers are supervisor-level SPRs. However, in the 750GX, the contents of these registers can be read by
user-level software using separate SPRs (UMMCR0 and UMMCR1). Control fields in the MMCR0 and
MMCR1 select the events to be counted, can enable a counter overflow to initiate a performance-monitor
exception, and specify the conditions under which counting is enabled.
As with other PowerPC exceptions, the performance-monitor interrupt follows the normal PowerPC exception
model with a defined exception vector offset (0x00F00). Its priority is below the external interrupt and above
the decrementer interrupt.
11.1 Performance-Monitor Interrupt
The performance monitor enables the generation of a performance-monitor interrupt triggered by a counter
overflow condition in one of the Performance-Monitor Counter Registers (PMC1–PMC4). A counter is consid-
ered to have overflowed when its most-significant bit is set. A performance-monitor interrupt can also be
caused by flipping certain bits from 0 to 1 in the Time Base Register, which provides a way to generate a time
reference-based interrupt.
Although the interrupt signal condition can occur with the external interrupt enable bit in the Machine State
Register (MSR[EE]) off, the actual exception cannot be taken until the MSR[EE] bit is on.