Filter
Top Products
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Bus Interface Operation
Page 316 of 377
gx_08.fm.(1.2)
March 27, 2006
8.6 Optional Bus Configuration
The 750GX supports optional bus configurations that are selected during the negation of the HRESET signal.
The operation and selection of the optional bus configuration are described in the following sections.
8.6.1 32-Bit Data Bus Mode
The 750GX supports an optional 32-bit data bus mode. The 32-bit data bus mode operates the same as the
64-bit data bus mode with the exception of the byte lanes involved in the transfer and the number of data
beats that are performed. When in 32-bit data bus mode, only byte lanes 0 through 3 are used corresponding
to DH0–DH31 and DP0–DP3. Byte lanes 4 through 7 corresponding to DL0–DL31 and DP4–DP7 are never
used in this mode. The unused data bus signals are not sampled by the 750GX during read operations, and
they are driven low during write operations.
The number of data beats required for a data tenure in the 32-bit data bus mode is one, two, or eight beats
depending on the size of the program transaction and the cache mode for the address. Data transactions of
one or two data beats are performed for caching-inhibited load/store or write-through store operations. These
transactions do not assert the TBST
signal even though a two-beat burst may be performed (having the same
TBST
and TSIZ[0–2] encodings as the 64-bit data bus mode). Single-beat data transactions are performed
for bus operations of 4 bytes or less, and double-beat data transactions are performed for 8-byte operations
only. The 750GX only generates an 8-byte operation for a double-word-aligned load or store double operation
to or from the Floating Point Registers. All cache-inhibited instruction fetches are performed as word (single-
beat) operations.
Data transactions of eight data beats are performed for burst operations that load into or store from the
750GX’s internal caches. These transactions transfer 32 bytes in the same way as in 64-bit data bus mode,
asserting the TBST
signal, and signaling a transfer size of 2 (TSIZ(0–2) = 0b010).
The same bus protocols apply for arbitration, transfer, and termination of the address and data tenures in the
32-bit data bus mode as apply to the 64-bit data bus mode. Late ARTRY
cancellation of the data tenure
applies on the bus clock after the first data beat is acknowledged (after the first TA
) for word or smaller trans-
actions, or on the bus clock after the second data beat is acknowledged (after the second TA
) for double-
word or burst operations (or coincident with respective TA
if no-DRTRY mode is selected).
An example of an eight-beat data transfer while the 750GX is in 32-bit data bus mode is shown in Figure 8-23
on page 317.