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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_02.fm.(1.2)
March 27, 2006
Programming Model
Page 97 of 377
Examples of uses of these instructions to perform various conversions can be found in Appendix D, “Floating-
Point Models,” in the PowerPC Microprocessor Family: The Programming Environments Manual.
Floating-Point Compare Instructions
Floating-point compare instructions compare the contents of two Floating Point Registers. The comparison
ignores the sign of zero (that is, +0 = –0).
The floating-point compare instructions are summarized in Table 2-15.
.
The PowerPC Architecture allows an fcmpu or fcmpo instruction with the record bit (Rc) set to produce a
boundedly-undefined result, which might include an illegal instruction program exception. In the 750GX, crfD
should be treated as undefined
Floating-Point Status and Control Register Instructions
Every FPSCR instruction appears to synchronize the effects of all floating-point instructions executed by a
given processor. Executing an FPSCR instruction ensures that all floating-point instructions previously initi-
ated by the given processor appear to have completed before the FPSCR instruction is initiated and that no
subsequent floating-point instructions appear to be initiated by the given processor until the FPSCR instruc-
tion has completed.
The FPSCR instructions are summarized in Table 2-16. For more information, see the PowerPC Micropro-
cessor Family: The Programming Environments Manual.
Table 2-14. Floating-Point Rounding and Conversion Instructions
Name Mnemonic Syntax
Floating Round to Single frsp (frsp.) frD,frB
Floating Convert to Integer Word fctiw (fctiw.) frD,frB
Floating Convert to Integer Word with Round
toward Zero
fctiwz (fctiwz.) frD,frB
Table 2-15. Floating-Point Compare Instructions
Name Mnemonic Syntax
Floating Compare Unordered fcmpu crfD,frA,frB
Floating Compare Ordered fcmpo crfD,frA,frB
Table 2-16. Floating-Point Status and Control Register Instructions
Name Mnemonic Syntax
Move-from FPSCR mffs (mffs.) frD
Move-to Condition Register from FPSCR mcrfs crfD,crfS
Move-to FPSCR Field Immediate mtfsfi (mtfsfi.) crfD,IMM
Move-to FPSCR Fields mtfsf (mtfsf.) FM,frB
Move-to FPSCR Bit 0 mtfsb0 (mtfsb0.) crbD
Move-to FPSCR Bit 1 mtfsb1 (mtfsb1.) crbD