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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_03.fm.(1.2)
March 27, 2006
Instruction-Cache and Data-Cache Operation
Page 137 of 377
Figure 3-5. PLRU Replacement Algorithm
Replace
L0
Replace
L1
Replace
L2
Replace
L3
Replace
L4
Replace
L5
Replace
L6
Replace
L7
B0 = 0
B4 = 0
B1 = 0 B1 = 1 B2 = 1B2 = 0
B0 = 1
B3 = 0 B3 = 1 B4 = 1 B5 = 0 B5 = 1 B6 = 0 B6 = 1
Allocate
L0
L0 invalid
Allocate
L2
L2 invalid
Allocate
L1
L1 invalid
Allocate
L3
L3 invalid
Allocate
L4
L4 invalid
Allocate
L5
L5 invalid
Allocate
L6
L6 invalid
Allocate
L7
L7 invalid
L7 valid
L0 valid
L1 valid
L2 valid
L3 valid
L4 valid
L5 valid
L6 valid