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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_09.fm.(1.2)
March 27, 2006
L2 Cache
Page 327 of 377
Figure 9-1. L2 Cache
60x Bus 64-bit
Bus Interface Unit
Data-Out Request Data-In Request
8-bit64-bit
L2 SRAM
1 MB
ECC ECCECC ECC
64-bit 64-b
it
Store
Queue
ST0, ST1,
3 Lines
L2
Reload
Queue
2 Lines
L1 Data Cache
Castout,
Single Beat Stores
L1 Data
Load Store
Instruction Cache
Reload
64-bit
256-bit
64-bit
72-bit
64-bit
64-bit
64-bit
64-bit
256-bit
Critical
Word
SNP
ECC
L2
Castout
Snoop
Queue
5 Lines
Cache
Reload