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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_06.fm.(1.2)
March 27, 2006
Instruction Timing
Page 239 of 377
Move-from Special
Purpose Register
mfspr (data
block-address
translations
[DBATs])
31 339 SRU 3 Execution
mfspr
(instruction
block-address
translations
[IBATs])
31 339 SRU 3 —
mfspr (not
I/DBATs)
31 339 SRU 1 Execution
Move-from Segment
Register
mfsr 31 595 SRU 3 —
Move-from Segment
Register Indirect
mfsrin 31 659 SRU 3 Execution
Move-from Time Base mftb 31 371 SRU 1 —
Move-to Machine State
Register
mtmsr 31 146 SRU 1 Execution
Move-to Special
Purpose Register
mtspr
(DBATs)
31 467 SRU 2 Execution
mtspr
(IBATs)
31 467 SRU 2 Execution
mtspr (not
I/DBATs)
31 467 SRU 2 Execution
Move-to Segment
Register
mtsr 31 210 SRU 2 Execution
Move-to Segment
Register Indirect
mtsrin 31 242 SRU 2 Execution
Move-to Time Base
Register
mttb 31 467 SRU 1 Execution
Return from Interrupt rfi 19 50 SRU 2 Completion, refetch
System Call sc 17 - -1 SRU 2 Completion, refetch
Synchronize sync 31 598 SRU 3
1
—
TLB Synchronize tlbsync
2
31 566 — —
Table 6-5. System-Register Instructions (Page 2 of 2)
Instruction Mnemonic
Primary
Opcode
Extended
Opcode
Unit Cycles Serialization
1. This 3-cycle operation assumes no pending stores in the store queue. If there are pending stores, the sync completes after the
stores complete to memory. If broadcast is enabled on the 60x bus, sync completes only after a successful broadcast.
2. tlbsync is dispatched only to the completion buffer (not to any execution unit) and is marked finished as it is dispatched. Upon
retirement, it waits for an external TLB Invalidate Synchronize (TLBISYNC
) signal to be asserted. In most systems, TLBISYNC is
always asserted so the instruction is a no-op.