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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Instruction-Cache and Data-Cache Operation
Page 124 of 377
gx_03.fm.(1.2)
March 27, 2006
3.2 Instruction-Cache Organization
The instruction cache also consists of 128 sets of eight ways, as shown in Figure 3-3 on page 125. Each way
consists of 32 bytes, a single state bit, and an address tag. As with the data cache, each instruction-cache
block contains eight contiguous words from memory that are loaded from an 8-word boundary (that is, bits
A[27–31] of the logical [effective] addresses are zero). As a result, cache blocks are aligned with page bound-
aries. Also, address bits A[20–26] provide the index to select a set, and bits A[27–29] select a word within a
block.
The tags consist of bits PA[0–19]. Address translation occurs in parallel with set selection (from A[20–26]),
and the higher order address bits (the tag bits in the cache) are physical.
The instruction cache differs from the data cache in that it does not implement MEI cache-coherency protocol,
and a single state bit is implemented that indicates only whether a cache block is valid or invalid. The instruc-
tion cache is not snooped, so if a processor modifies a memory location that might be contained in the
instruction cache, software must ensure that such memory updates are visible to the instruction-fetching
mechanism. This can be achieved with the following instruction sequence:
dcbst # update memory
sync # wait for update
icbi # remove (invalidate) copy in instruction cache
sync # wait for the Instruction Cache Block Invalidate (ICBI) operation to be globally performed
isync # remove copy in own instruction buffer
These operations are necessary because the processor does not maintain instruction memory coherent with
data memory. Software is responsible for enforcing coherency of instruction caches and data memory.
Since instruction fetching might bypass the data cache, changes made to items in the data cache might not
be reflected in memory until after the instruction fetch completes.