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REAL ADDRESS MODE
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T
6
l
4K
SEGMENT
B
T
-
..
-_~_V_;_LA_-;_-t
--
......
BASE
OF
SEGMENTB
-'1
t------t--
BASE
OF
SEGMENT
A
,
Figure
5-2.
Overlapping
Segments
to
Save
Physical
Memory
5.2
INTERRUPT
HANDLING
G30108
Program interrupts may be generated
in
either of
two
distinct
ways.
An internal interrupt
is
caused
directly by the currently executing program. The execution of a particular instruction results in the
occurrence of an interrupt, whether intentionally (e.g., an INT n instruction) or
as
an unanticipated
exception (e.g., invalid opcode).
On the other hand, an external interrupt occurs asynchronously
as
the
result of an event external to the processor, and bears
no
necessary relationship with the currently
executing program. The
INTR
and
NMI
pins of the 80286 provide the means
by
which
external
hardware signals the occurrence of such events.
5.2.1 Interrupt Vector Table
Whatever its origin, whether internal or external, an interrupt demands immediate attention from an
associated service routine. Control must be transferred, at least for the moment, from the currently
executing program to the appropriate interrupt service routine.
By
means of interrupt vectors, the
80286 handles such control transfers uniformly for both kinds of interrupts.
An interrupt vector
is
an unsigned integer in the range of 0-255; every interrupt
is
assigned such a
vector. In some cases, the assignment
is
predetermined and fixed: for example, an external
NMI
inter-
rupt
is
invariably associated with vector
2,
while an internal divide exception
is
always associated with
vector
O.
In most cases, however, the association of an interrupt and a vector
is
established dynami-
cally. An external
INTR
interrupt, for example, supplies a vector in response
to
an interrupt acknowl-
edge bus cycle, while the
INT
n instruction supplies a vector incorporated within the instruction itself.
The vector
is
shifted
two
places left to form a byte address into the table (see figure
5-3).
In any case, the 80286 uses the interrupt vector
as
an index into a table in order to determine the
address of the corresponding interrupt service routine. For Real Address Mode, this table
is
known
as
the Interrupt Vector Table. Its format
is
illustrated
in
figure
5-3.
5-3