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PROGRAMMING NUMERIC APPLICATIONS
Instruction synchronization
is
guaranteed for most
ESC
instructions because the 80286 automatically
checks the
BUSY
status line from the 80287 before commencing execution
of
most
ESC
instructions.
No
explicit
WAIT
instructions
are
necessary to ensure proper instruction synchronization.
Data Synchronization
Data
synchronization addresses the issue
of
both the
CPU
and the
NPX
referencing the same memory
values within a given block
of
code. Synchronization ensures
that
these two processors access the memory
operands in the proper sequence, just as they would be accessed by a single processor with no concur-
rency.
Data
synchronization
is
not a concern when the
CPU
and
NPX
are using different memory
operands during the course
of
one numeric instruction.
The
two cases where
data
synchronization might be a concern are
1.
The
80286
CPU
reads or alters a memory operand first, then invokes the 80287 to load or
alter
the
same operand.
2.
The
80287
is
invoked to load or alter a memory operand, after which the 80286 CPU reads
or
alters the same location.
Due
to the instruction synchronization of the
NPX
interface,
data
synchronization
is
automatically
provided for the first
case-the
80286 will always complete its operation before invoking the 80287.
For the second case,
data
synchronization
is
not always automatic. In general, there
is
no
guarantee
that
the 80287 will have finished its processing and accessed the memory operand before the 80286
accesses the same location.
Figure 2-9 shows examples of the two possible cases
of
the
CPU
and
NPX
sharing a memory value. In
the examples
of
the first case, the
CPU
will finish with the operand before the 80287 can reference it.
The
NPX
interface guarantees this. In the examples of the second case, the
CPU
must wait for the
80287 to finish with the memory operand before proceeding to reuse it. The
FW
AIT
instructions shown
in these examples are required in order to ensure this
data
synchronization.
There are several
NPX
control instructions where automatic
data
synchronization
is
provided; however,
the
FSTSW
/FNSTSW,
FSTCW
/FNSTCW,
FLDCW,
FRSTOR,
and
FLDENV
instructions
are
all
guaranteed to finish their execution before the
CPU
can read or alter the referenced memory locations.
The
80287 provides
data
synchronization for these instructions by making a request on the Processor
Extension
Data
Channel before the
CPU
executes its next instruction. Since the
NPX
data transfers
occur before the
CPU
regains control
of
the local bus, the
CPU
cannot change a memory value before
the
NPX
has had a chance to reference it. In the case
of
the
FSTSW
AX
instruction, the 80286
AX
register
is
explicitly updated before the
CPU
continues execution
of
the next instruction.
For
the
numeric instructions not listed above, the assembly-language programmer must remain aware
of synchronization and recognize cases requiring explicit
data
synchronization.
Data
synchronization
can be provided either by programming an explicit
FW
AIT
instruction, or by initiating a subsequent
numeric instruction before accessing the operands
or
results of a previous instruction. After the subse-
quent numeric instruction has started execution, all memory references in earlier numeric instructions
are
complete. Reaching the next host instruction
after
the synchronizing numeric instruction indicates
that
previous numeric operands in memory
are
available.
2-49