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INTERRUPTS AND EXCEPTIONS
9.7.1 Single Step Interrupt (Interrupt 1)
Interrupt 1 allows programs
to
execute one instruction
at
a time. This single-stepping
is
controlled by
the
TF
bit in the flag word. Once this bit
is
set, an internal single step interrupt
will
occur after the
next instruction has been executed. The interrupt saves the flags' and return address on the stack, clears
theTF
bit, and uses an internally supplied vector of 1
to
transfer control to the service routine via the
IDT.
The
IRET
instruction or a task switch must be used to set the
TF
bit and to transfer control
to
the
next instruction to be single stepped.
If
TF=
1
in
a TSS and that task
is
invoked, it
will
execute the
first instruction
and then be interrupted.
The single-step flag
is
normally not cleared
by
privilege changes inside a task.
INT
instructions, however,
do
clear TF. Therefore, software debuggers that single-step code must recognize and emulate
INT
n
or
INT
0 rather than executing them directly. System software should check the current execution
privilege level after any single step interrupt
to
see whether single stepping should continue.
The interrupt priorities
in
hardware guarantee that if an external interrupt occurs, single stepping
stops. When both an external interrupt and a single step interrupt occur together, the single step inter-
rupt
is
processed first. This clears the
TF
bit.
After
saving the return address or switching tasks, the
external interrupt input
is
examined before the first instruction of the single step handler executes.
If
the external interrupt
is
still pending, it
is
then serviced. The external interrupt handler
is
not single-
stepped. Therefore, to single step an interrupt handler, just single step an interrupt instruction that
refers to the interrupt handler.,
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