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INTERRUPTS
AND
EXCEPTIONS
-
OLD
SP
NO
PRIVILEGE
TRANSITION
OLD
FLAGS
OLD
CS
OLD
IP
ERROR
CODE
SP
,"
"
SP
FROM
TSS
- -
WITH
PRIVILEGE
TRANSITION
OLD
SS
OLDSP
OLD
FLAGS
OLDCS
OLD
IP
ERROR
CODE
SP
"
"
SSFROMTSS--~.~'r~------
______
~l!
STACK
SEGMENT
G30108
Figure 9-4. Stack Layout after
an
Exception with
an
Error Code
If
an interrupt gate
is
used
to
handle an interrupt, it
is
assumed that the selected code segment has
sufficient privilege to re-enable interrupts. The IRET instruction
will
not re-enable interrupts if CPL
is
numerically greater than IOPL.
Table
9-1
shows the checks performed during an interrupt operation that uses an interrupt or trap gate.
EXT equals 1 when an event external to the program
is
involved; 0 otherwise. EJ\ternal events are
maskable
or
non-maskable interrupts, single step interrupt, processor extension segment overrun inter-
rupt, numeric processor not-present exception or numeric processor error. The EXT bit signals that the
interrupt or exception
is
not related to the instruction
at
CS:IP. Each error code has bit 1 set to indicate
an IDT entry
is
involved.
When the interrupt has been serviced, the service routine returns control via an IRET instruction to
the routine that
was
interrupted.
If
an error code
was
passed, the exception handler must remove the
error code from the stack before executing IRET.
The
NT
flag
is
cleared when an interrupt occurs which uses an interrupt or trap gate. Executing IRET
with
NT=O
causes the normal interrupt return function. Executing
IRET
with
NT=
leauses
a task
switch (see section 8
.4
for more details).
9-5