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SYSTEM-LEVEL NUMERIC PROGRAMMING
As
discussed previously, the 80287
NPX
can take one of
two
actions
when
it recognizes a numeric
exception:
•
If
the exception
is
masked, the NPX
will
automatically perform its
own
masked exception response,
correcting the exception condition according to fixed rules, and then continuing with its instruction
execution.
•
If
the exception
is
unmasked, the
NPX
signals the exception to the 80286
CPU
using the
ERROR
status line between the
two
processors. Each time the 80286 encounters an ESC or WAIT instruc-
tion in its instruction stream, the
CPU checks the condition of this
ERROR
status line. If
ERROR
is
active, the
CPU
automatically traps to Interrupt vector #16, the Processor Extension Error trap.
Interrupt vector #16 typically points
to
a software exception handler, which
mayor
may
not
be a part
of systems software. This exception handler takes the form of an 80286 interrupt procedure.
When handling numeric errors, the
CPU has
two
responsibilities:
• The CPU must not disturb the numeric context when an error
is
detected.
• The CPU must clear the error and attempt recovery from the error.
Although the manner in which programmers may treat these responsibilities varies from
one
imple-
mentation to the next, most exception handlers
will
include these basic steps:
• Store the
NPX
environment (control, status, and tag words, operand and instruction pointers) as it
existed
at
the time of the exception.
• Clear the exception bits
in
the status word.
• Enable interrupts
on
the CPU.
•
Identify the exception by examining the status and control words
in
the save environment.
• Take some system"dependent action to rectify the exception.
• Return to the interrupted program and resume normal execution.
It
should be noted
that
the NPX exception pointers contained
in
the stored
NPX
environment
will
take
different forms, depending
on
whether the
NPX
is
operating
in
Real-Address mode or in Protected
mode. The earlier discussion of Real versus Protected mode details
how
this information
is
presented
in
each of the
two
operating modes.
Simultaneous
Exception
Response
In cases where multiple exceptions arise simultaneously, the 80287 signals one exception according to
the precedence sequence shown in table
3-2.
This means, for example, that zero divided by zero
will
result in an invalid operation, and not a zero divide exception.
Exception Recovery
Examples
Recovery routines for
NPX
exceptions can take a variety of forms. They can change the arithmetic
and programming rules of the
NPX. These changes may redefine the default fix-up for an error, change
the appearance of the
NPX
to the programmer, or change
how
arithmetic
is
defined
on
the NPX.
A change to an error response might be to automatically normalize all denormals loaded from memory.
A change
in
appearance might be extending the register stack into memory to provide an "infinite"
3-7