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CHAPTER 8
TASKS
AND
5T
ATE TRANSITIONS
8.1 INTRODUCTION
An 80286 task
is
a single, sequential thread of execution. Each task can be isolated from all other
tasks. There may be many tasks associated with an
80286 CPU, but only one task executes
at
any
time. Switching the
CPU from executing one task to executing another can occur
as
the result of either
an interrupt or an inter-task CALL,
JMP
or
IRET. A hardware-recognized data structure defines each
task.
The 80286 provides a high performance task switch/operation with complete isolation between tasks.
A full task-switch operation takes only 22 microseconds at 8 MHz (18 microseconds at
10
MHz). High-
performance, interrupt-driven, multi-application systems that need the benefits of protection are feasi-
ble with the
80286.
A performance advantage and system design advantage arise from the 80286 task switch:
Faster task switch: A task switch
is
a single instruction performed by microcode. Such a scheme
is
2-3
times faster than an explicit task switch instruction. A fast task switch translates to a signif-
icant performance boost for heavily multi-tasked systems over conventional methods.
More reliable, flexible systems: The isolation between tasks and the high speed task switch allows
interrupts to be handled by separate tasks rather than within the currently interrupted task. This
isolation of interrupt handling code from normal programs prevents undesirable interactions between
them. The interrupt system can become more flexible since adding an interrupt handler
is
as safe
and easy
as
adding a new task.
Every task
is
protected from all others via the separation of address spaces described in
Chapter
7,
including allocation of unique stacks to each active privilege level
in
each task (unless
explicit sharing
is
planned
in
advance).
If
the address spaces of
two
tasks include
no
shared data,
one task cannot affect the data of another task. Code sharing
is
always safe since
code
segments
may never be written into.
8.2
TASK STATE SEGMENTS
AND
DESCRIPTORS
Tasks are defined by a special control segment called a Task State Segment (TSS). For each task,
there must be an unique TSS. The definition of a task includes its address space and execution state.
A task
is
invoked (made active) by inter-segment jump or call instructions whose destination address
refers to a task state segment or a task gate.
The Task State Segment (TSS) has a special descriptor. The Task Register within the
CPU contains
a selector to that descriptor. Each TSS selector value
is
unique, providing an unambiguous "identifier"
for each task. Thus, an operating system can use the value of the TSS selector to uniquely identify the
task.
A TSS contains
22
words that define the contents of all registers and flags, the initial stacks for privi-
lege levels
0-2,
the LDT selector, and a link
to
the TSS of the previously executing task. Figure
8-1
shows the layout of the TSS. The TSS can not
be
written into like an ordinary data segment.
8-1