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80286
BASE
ARCHITECTURE
The exceptions are: divide error,
INTO
detected overflow, bounds check, segment overrun, invalid
operation code,
and processor extension error (see table 2-4). A divide error exception results when
the instructions DIY or
IDlY
are executed with a zero denominator; otherwise, the quotient
will
be too
large for the destination operand (see section 3.3.4 for a discussion of DIY and IDlY). An overflow
exception results when the
INTO
instruction
is
executed and the OF flag
is
set (after
an
arithmetic
operation that set the overflow (OF) flag).
(See section 3.6.3, "Software Generated Interrupts," for a
discussion of INTO.) A bounds check exception results when the
BOUND instruction
is
executed and
the array index
it
checks falls outside the bounds of the array. (See section 4.2 for a discussion of the
BOUND instruction.) The segment overrun exception occurs when a word memory reference
is
attempted which extends beyond the end of a segment. An invalid operation code exception occurs
if
an attempt
is
made to execute an undefined instruction operation code. A processor extension error
is
generated when a processor extension detects an illegal operation. Refer
to
Chapter 5 for a more complete
description of these exception conditions.
The instruction
INT
generates an internal interrupt whenever
it
is
executed. The effects of this inter-
rupt (and the effects of all interrupts)
is
determined by the interrupt handler routines provided by the
application program or as part of the system software (provided by system programmers).
See
Chapter 5 for more
on
this topic. The
INT
instruction itself
is
discussed in section 3.6.3.
In
Protected Mode, many more fault conditions are detected and result in internal interrupts. Protected
Mode interrupts and faults are discussed in Chapter
9.
2.7
HIERARCHY
OF
INSTRUCTION
SETS
For descriptive purposes, the 80286 instruction set
is
partitioned into three distinct subsets: the Basic
Instruction
Set, the Extended Instruction Set, and the System Control Instruction Set. The "hierar-
chy"
of instruction sets defined
by
this partitioning helps
to
clarify the relationships between the various
processors in the
8086 family (see figure 2-15).
The Basic Instruction
Set, presented in Chapter 3, comprises the common subset of instructions found
on all processors of the
8086 family. Included are instructions for logical and arithmetic operations,
data movement, input/output, string manipulation, and transfer of control.
The Extended Instruction
Set, presented in Chapter
4,
consists of those instructions found only
on
the
80186, 80188, and 80286 processors. Included are instructions for block structured procedure entry
and exit, parameter validation, and block
I/O
transfers.
The
System Control Instruction Set, presented in Chapter
10,
consists of those instructions-,unique to
the
80286. These instructions control the memory management and protection mechanisms of the 80286.
2-25