Filter
Top Products
INTERRUPTS AND EXCEPTIONS
All but two exceptions are restartable after the exceptional condition
is
removed. The
two
non-
restartable exceptions are the processor extension segment overrun and writing into read only segments
with XCHG, ADC,
SBB, RCL, and
RCR
instructions. The return address normally points to the
failing instruction, including all leading prefixes.
The instruction and data addresses for the processor extension segment overrun are contained
in
the
processor extension status registers.
Interrupt handkrs
for
most exceptions receive an error code that identifies. the selector involved, or a
° in bits
15-3
of the error code field if there
is
no
selector involved. The error code
is
pushed last, after
the return address,
on
the stack that
will
be active when the trap handler begins execution. This ensures
that the handler
will
not have
to
access another stack segment to find the error code.
The following sections describe the exceptions
in
greater detail.
9.6.1 Invalid OP-Code (Interrupt 6)
When an invalid opcode
is
detected
by
the execution unit, interrupt 6
is
invoked.
(It
is
not detected
until an attempt
is
made to execute it, i.e., prefetching an invalid opcode
does
not cause this exception.)
The saved
CS:IP will point
to
the invalid opcode or any leading prefixes;
no
error code
is
pushed
on
the stack. The exception can be handled within the same task, and
is
restartable.
This exception will occur for all cases of an invalid operand. Examples include an inter-segment jump
referencing a register operand, or an
LES instruction with a register source operand.
9.6.2
Double Fault (Interrupt 8)
If
two
separate faults occur during a single instruction, end if the first fault
is
any of
#0,
#10, #11, #12,
and #13, exception 8 (Double Fault) occurs (e.g., a general protection fault
in
level 3
is
followed by a
not-present fault due
to
a segment not-present).
If
another protection violation occurs during the
processing of exception
8,
the 80286 enters shutdown, during which time
no
further instructions or
exceptions are processed.
Either
NMI
or RESET can force the CPU out
,of
shutdown. An
NMI
input
can
bring the CPU out of
shutdown if
no
errors occur while processing the
NMI
interrupt; otherwise, shutdown can only
be
exited via the RESET input.
NMI
causes the CPU
to
remain
in
protected mode, and RESET causes
it
to
exit protected mode. Shutdown
is
signaled externally
via
a
HALT
bus operation with
Al
LOW.
A task gate must
be
used for the double fault handler
to
assure a proper task state
to
respond to the
exception. The back link field in the current
TSSwill identify the TSS of the task causing the excep-
tion. The saved address will point
at
the instruction that
was
being executed (or
was
ready
to
execute)
when the error
was
detected. The error code will be null.
The
"double fault" exception does not occur
whim
detecting a
new
exception while trying
to
invoke
handlers for the following exceptions: 1,2,3,4,5,6,7,9, and
16
..
9.6.3
Processor Extension Segment Overrun (Interrupt 9)
Interrupt 9 signals that the processor extension (such
as
the 80287 numerics processor) has overrun
the limit of a segment while attempting to read/write the second or subsequent words of
an
operand.
9-10