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COMPATIBILITY CONSIDERATIONS
13.
Do not Rely
on
IDIV Exceptions for Quotients of 80H or 8000H.
The 80286 can generate the largest negative number
as
a quotient for IDIV instructions. The 8086
will
instead cause exception
O.
14.
Do not Rely
on
NMI
Interrupting
NMI
Handlers.
After an
NMI
is
recognized, the
NMI
input and processor extension limit error interrupt
is
masked
until the first
IRET
instruction
is
executed.
15.
The
NPX
error signal does not pass through an interrupt controller (an 8087
INT
signal does).
Any interrupt controller-oriented instructions for the
8087 may have to be deleted.
16.
If
any real-mode program relies
on
address space wrap-around (e.g., FFFO:0400=0000:0300),
then external hardware should be used to force the upper 4 addresses to zero during real mode.
17.
Do not use
I/O
ports 00F8-00FFH. These are reserved for controlling 80287 and future processor
extensions.
HARDWARE
COMPATIBILITY
CONSIDERATIONS
l.
Address after Reset
8086 has CS:IP =
ffff:OOOO
and physical address
ffffO.
80286 has CS:IP =
fOOO:fffO
and physical address
fffffO.
Note: After 80286 reset, until the first 80286 far
JMP
or far CALL, the code segment base
is
ffOOOO.
This means A20-A23
will
be high for CS-relative bus cycles (code fetch or use of
CS
override prefix) after reset until the first far
JMP
or far CALL instruction
is
performed.
2.
Physical Address Formation
In real mode or protected mode, the
80286 always forms a physical address by adding a l6-bit
offset with a 24-bit segment base value
(8086 has 20-bit base value). Therefore, if the 80286 in
real mode has a segment base within 64K of the top of the 1 Mbyte address space, and the program
adds an offset of ffffh to the segment base, the physical address
will
be slightly above IMbyte.
Thus, to fully duplicate 1 Mbyte wraparound that the
8086 has, it
is
always necessary to force A20
low
externally when the 80286
is
in
real mode, but system hardware uses all 24 address lines.
3.
LOCK signal
On the 8086, LOCK asserted means this bus cycle
is
within a group of
two
or more locked bus
cycles.
On the 80286, the LOCK signal means lock this bus cycle
to
the
NEXT
bus cycle. There-
fore, on the
80286, the LOCK signal
is
not asserted
on
the last locked bus cycle of the group of
locked bus cycles.
4.
Coprocessor Interface
8086, synchronous to 8086, can become a bus master.
80287, asynchronous to 80286 and 80287, cannot become a bus master.
8087 pulls opcode and pointer information directly from data bus.
80286 passes opcode and pointer information to 80287.
8087
uses interrupt path to signal errors to 8086.
80287
uses dedicated
ERROR
signal.
8086 requires explicit WAIT opcode preceding all
ESC
instructions
to
synchronize with 8087.
80286
has automatic instruction synchronization with 80287.
5.
Bus Cycles
8086 has four-clock minimum bus cycle, with a time-multiplexed address/data bus.
80286 has two-clock minimum bus cycle, with separate buses for address and data.
C-3