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INTERRUPTS AND EXCEPTIONS
The interrupt
is
generated by the processor extension data channel within the 80286 during the limit
test performed
on
each transfer of data between memory and the processor extension. This interrupt
can be handled
in
the same task but
is
not restartable.
As
with all external interrupts, Interrupt 9
is
an asynchronous demand caused by the processor exten-
sion referencing something outside a segment boundary.
Since Interrupt 9 can occur any time after
the processor extension
is
started, the 80286 does not save any information that identifies what partic-
ular operation had been initiated
in
the processor extension. The processor extension maintains special
registers that identify the last instruction it executed and the address of the desired operand.
After this interrupt occurs,
no
WAIT or escape instruction, except
FNINIT,
can be executed until the
interrupt condition
is
cleared or the processor extension
is
reset. The interrupt signals that the processor
extension
is
requesting an invalid data transfer. The processor extension
will
always
be
busy when
waiting
on
data. Deadlock results if the CPU executes an instruction that causes it
to
wait for the
processor extension before resetting the processor extension. Deadlock means the
CPU
is
waiting for
the processor extension
to
become idle while the processor extension waits for the CPU to service its
data request.
The
FNINIT
instruction
is
guaranteed to reset the processor extension without causing deadlock. After
the interrupt
is
cleared, this restriction
is
lifted.
It
is
then possible to read the instruction and operand
address via
FSTENV or FSA VE, causing the segment overrun
in
the processor extension's special
registers.
The task interrupted by interrupt
9
is
not necessarily the task that executed the
ESC
instruction that
caused the interrupt. The operating system should keep track of which task last used the
NPX
'(see
section 11.4).
If
the interrupted task did not execute the ESC instruction, it can be restarted. The task
that executed the ESC instruction cannot.
9.6.4
Invalid Task State Segment (Interrupt 10)
Interrupt
10
is
invoked if during a task switch the
new
TSS pointed to by the task gate
is
invalid. The
EXT bit indicates whether the exception
was
caused by an event outside the control of the program.
A
TSS
is
considered invalid
in
the cases shown
in
table
9-5.
Once the existence of the
new
TSS
is
verified, the task switch
is
considered complete, with the backlink
set to the old task if necessary.
All
errors are handled
in
the context of the
new
task.
Exception
10
must be handled through a task gate to insure a proper TSS to process it. The handler
must reset the busy bit
in
the newTSS.
9.6.5
Not Present (Interrupt 11)
Exception
II
occurs when
an
attempt
is
made to load a not-present segment
or
to
use.
a control descrip-
tor that
is
marked not-present.
(If,
however, the missing segment
is
an LDT that
is
needed
in
a task
switch, exception
10
occurs.) This exception
is
fully restartable.
Any segment load instruction can cause this exception. Interrupt
11
is
always processed
in
the context
of the task
in
which it occurs.
9-11