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11.4
NPX CONTEXT SWITCHING
The context of a processor extension (such
as
the 80287 numerics processor)
is
not changed
by
the task
switch operation. A processor extension context need only
be
changed when a different task attempts
to use the processor extension (which still contains the context of a previous task). The
80286
detects
the first use of a processor extension after a task switch
by
causing the processor extension not-present
exception (#7) if the TS bit
is
set. The interrupt handler may then decide whether a context change
is
necessary.
The 286 services numeric errors only when it executes wait or escape instructions because the processor
extension
is
running independently. Therefore, the numerics error from
one
task may not
be
recorded
until the 286
is
running a different task.
If
the 286 task has changed,
it
makes sense
to
defer handling
that error until the original task
is
restored. For example, interrupt handlers that use the NPX should
not have their timing upset
by
a numeric error interrupt that pertains
to
some earlier process.
It
is
of
little value
to
service someone else's error.
If
the task switch bit
is
set (bit 3 of MSW) when the CPU begins
to
execute a wait or escape instruc-
tion, the processor-extension not-present exception results (#7). The handler for this interrupt must
know
who
currently "owns" the NPX, i.e., the handler must
know
the last task
to
issue a command
to
the NPX.
If
the owner
is
the same as the current task, then it
was
merely interrupted and the interrupt
handler has since returned; the handler for interrupt 7 simply clears the TS bit, restores the working
registers, and returns (restoring interrupts if enabled).
If
the recorded owner
is
different from the current task, the handler must first save the existing
NPX
context in the save area of the old task.
It
can then re-establish the correct NPX context from the
current task's save area.
The code example
in
figure
11-3
relies on the convention that each TSS entry in the GDT
is
followed
by
an alias entry for a data segment that points
to
the same physical region of memory that contains
the TSS. The alias segment also contains
an
area for saving the NPX context, the kernel stack, and
certain kernel data. That
is,
the first
44
bytes
in
that segment are the
286
context, followed
by
94
bytes
for the processor extension context, followed
in
some cases by the kernel stack and kernel private
data areas.
The implied convention
is
that the stack segment selector points
to
this data segment alias
so
that
whenever there
is
an interrupt at level zero and SS
is
automatically loaded, all of the above information
is
immediately addressable.
It
is
assumed that the program example
knows
about only
one
data segment that points
to
a global
data area
in
which it can find the one word NPX owner
to
begin the processing described. The specific
operations needed, and shown
in
the figure, are listed
in
table
11-1.
11.5
MULTIPROCESSOR CONSIDERATIONS
As
mentioned
in
Chapter
8,
a bus lock
is
applied during the testing and setting of the task busy bit
to
ensure that
two
processors
do
not invoke the same task at the same time. However, protection traps
and conflicting use of dynamically varying segments or descriptors must
be
addressed
by
an inter-
processor synchronization protocol. The protocol can use the indivisible semaphore operation of the
base instruction set. Coordination of interrupt and trap vectoring must also
be
addressed
when
multiple
concurrent processors are operating.
The.
interrupt bus cycles are locked
so
no
interleaving occurs
on
those cycles. Descriptor caching
is
locked
so
that a descriptor reference cannot
be
altered while it
is
being fetched.
11-5