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CHAPTER 5 CPU ARCHITECTURE
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all
other cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0, the
vectored interrupt whose priority is specified by the priority specify flag registers (PR0L, PR0H, and PR1L)
(Refer to 21.3 (3) Priority specify flag registers (PR0L, PR0H, and PR1L)) to be low is disabled.
Whether the interrupt is actually acknowledged is controlled by the status of the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area. The following shows the internal high-speed RAM area of each product.
Table 5-4. Internal High-Speed RAM Area
Part Number Internal High-Speed RAM Area
µ
PD78052, 78052Y FD00H to FEFFH
µ
PD78053, 78053Y FB00H to FEFFH
µ
PD78054, 78054Y
µ
PD78P054
µ
PD78055, 78055Y
µ
PD78056, 78056Y
µ
PD78058, 78058Y
µ
PD78P058, 78P058Y