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LIST OF FIGURES (8/8)
Figure No. Title Page
23-3. HALT Mode Release by RESET Input........................................................................................... 529
23-4. STOP Mode Release by Interrupt Request Generation ................................................................ 531
23-5. Release by STOP Mode RESET Input.......................................................................................... 532
24-1. Block Diagram of Reset Function.................................................................................................. 533
24-2. Timing of Reset Input by RESET Input.......................................................................................... 534
24-3. Timing of Reset due to Watchdog Timer Overflow ........................................................................ 534
24-4. Timing of Reset Input in STOP Mode by RESET Input ................................................................. 534
25-1. Block Diagram of ROM Correction ................................................................................................ 537
25-2. Correction Address Registers 0 and 1 Format .............................................................................. 538
25-3. Correction Control Register Format .............................................................................................. 539
25-4. Storing Example to EEPROM (when one place is corrected) ....................................................... 540
25-5. Connecting Example with EEPROM (using 2-wire serial I/O mode) ............................................. 540
25-6. Initialization Routine ...................................................................................................................... 541
25-7. ROM Correction Operation............................................................................................................ 542
25-8. ROM Correction Example ............................................................................................................. 543
25-9. Program Transition Diagram (when one place is corrected) ......................................................... 544
25-10. Program Transition Diagram (when two places are corrected) ..................................................... 545
26-1. Memory Size Switching Register Format (
µ
PD78P054) ............................................................... 549
26-2. Memory Size Switching Register Format (
µ
PD78P058) ............................................................... 550
26-3. Internal Expansion RAM Size Switching Register Format ............................................................ 551
26-4. Page Program Mode Flowchart..................................................................................................... 554
26-5. Page Program Mode Timing.......................................................................................................... 555
26-6. Byte Program Mode Flowchart...................................................................................................... 556
26-7. Byte Program Mode Timing ........................................................................................................... 557
26-8. PROM Read Timing ...................................................................................................................... 558
B-1. Development Tool Configuration ................................................................................................... 580
B-2. EV-9200GC-80 Drawing (For Reference Only) ............................................................................. 590
B-3. EV-9200GC-80 Footprint (For Reference Only) ............................................................................ 591
B-4. TGK-080SDW Drawing (For Reference) (unit: mm)...................................................................... 592