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CHAPTER 25 ROM CORRECTION
7
0
6
0
5
0
4
0
COREN1 CORST1 COREN0 CORST0
Symbol
CORCN
Address
FF8AH
State
after reset
COREN0
0
1
CORST0
0
1
COREN1
0
1
CORST1
0
1
R/W
R/W
Note
00H
Correction address register 0 and fetch address match detection
Not detected
Detected
Correction address register 0 and fetch address match
detection control
Disabled
Enabled
Correction address register 1 and fetch address match detection
Not detected
Detected
Correction address register 1 and fetch address match
detection control
Disabled
Enabled
<3> <2> <1> <0>
25.3 ROM Correction Control Registers
The ROM correction is controlled with the correction control register (CORCN).
(1) Correction control register (CORCN)
This register controls whether or not the correction branch request signal is generated when the fetch
address matches the correction address set in correction address registers 0 and 1. The correction control
register consists of correction enable flags (COREN0, COREN1) and correction status flags (CORST0,
CORST1). The correction enable flags enable or disable the comparator match detection signal, and
correction status flags show the values are matched. CORCN is set with a 1-bit or 8-bit memory manipulation
instruction.
RESET input sets CORCN to 00H.
Figure 25-3. Correction Control Register Format
Note Bits 0 and 2 are read-only bits.